DC-DC converter

ABSTRACT

A DC—DC converter that receives input of a direct current voltage such as a battery and supplies a controlled direct current voltage to a load is simplified. It comprises a voltage step-down converter section consisting of a first switch  2 , a first rectifying means  3  and an inductor  4 , a voltage step-up converter section consisting of an inductor  4 , a second switch  5  and a second rectifying means  6 , and a control section consisting of an output capacitor  7 , an error amplifying circuit  10 , an oscillation circuit  11  and a pulse width control circuit  12 . An oscillation voltage Vt from the oscillation circuit  11  is compared with an error voltage Ve from the error amplifying circuit  10  and a duty ratio of each switch is adjusted to control the operation of voltage step-down, voltage step-up and step-down, and voltage step-up.

CROSS-REFERENCE TO RELATED APPLICATION

This application is a Section 371 of International Application No.PCT/JP02/13044, filed Dec. 12, 2002, the disclosure of which isincorporated herein by reference.

TECHNICAL FIELD

The present invention relates to a DC—DC converter which is used forvarious electronic apparatuses, receives a direct current voltage inputfrom a battery or the like and supplies a controlled direct currentvoltage to a load, and more particularly relates to a DC—DC convertercapable of carrying out voltage step-up and step-down in an input andoutput noninverting state.

BACKGROUND ART

FIG. 10( a) and FIG. 10( b) show a prior art of a DC—DC converter forstepping up or stepping down a direct current voltage input from adirect current power source such as a battery in an input and outputnoninverting state (the state wherein the polarity of the direct currentinput voltage is the same as that of the direct current output voltage)and supplying the direct current voltage to a load (See Japanese PatentNo. Sho 58-40913). Voltage step-up is to output a direct current outputvoltage higher than a direct current input voltage, and voltagestep-down is the reverse thereto. FIG. 10( a) is a circuit diagram ofthe above-mentioned DC—DC converter disclosed as the prior art, and FIG.10( b) is a waveform diagram showing signals at each section thereofduring the operation.

As shown in FIG. 10( a), this DC—DC converter is connected to a directcurrent input power source 31 for a voltage Ei and provided with avoltage step-down converter section consisting of a first switch 32, afirst diode 33 and an inductor 34, a step-up converter sectionconsisting of a second switch 35 and a second diode 36, having theinductor 34 in common, and an output capacitor 37. A voltage Eo of theoutput capacitor 37 is applied to a load 38 as a direct current outputvoltage.

As shown in FIG. 10( b), the first switch 32 and the second switch 35are turned ON and OFF in the same switching cycle-T. The ratios of ONtime of the first switch 32 and the second switch 35 per one switchingcycle are referred to as a duty ratio δ 1 and a duty ratio δ2,respectively. As shown in the figure, the duty ratio δ1 is made largerthan the duty ratio δ2: (δ1>δ).

When both the first switch 32 and the second switch 35 remain ON, thevoltage Ei of the direct current input power source 31 is applied to theinductor 34. The time of application is the product of the duty ratio 2by the switching cycle T: (δ2·T). At this time, a current flows from thedirect current input power source 31 to the inductor 34, wherebymagnetic energy is stored. Next, when the second switch 35 turns OFF,the second diode 36 becomes conductive, and the voltage that is adifference between the direct current input voltage Ei and the directcurrent output voltage Eo: (Ei−Eo) is applied to the inductor 34. Thetime of application is a difference between the product of the dutyratio δ1 by the switching cycle T, and the product of the duty ratio δ2by the switching cycle T: (δ1·T−δ2·T). During the time of application, acurrent flows from the DC input power source 31 to the output capacitor37 via the inductor 34. Further, when the first switch 32 turns OFF, thefirst diode 33 becomes conductive, and the direct current output voltageEo is applied to the inductor 34 in the opposite direction. This time ofapplication is a time (T−δ1·T), and a current flows from the inductor 34to the output capacitor 37, whereby the stored magnetic energy isreleased.

As mentioned above, by repeating the operation of storage and release ofthe magnetic energy, electric power is supplied from the outputcapacitor 37 to the load 38. In a stable operation state wherein thestorage and release of the magnetic energy of the inductor 34 balances,the sum of the products of the applied voltages and times of applicationis zero as represented by equation (1).Ei·δ2·T+(Ei−Eo)(δ1·T−δ2·T)−Eo(T−δ1·T)=0  (1)

By arranging this equation, a conversion characteristic equationrepresented by equation (2) is obtained.Eo/Ei=δ1/(1−δ2)  (2)

When the duty ratio δ2 is 0: (δ2=0), the ratio Eo/Ei of the directcurrent output voltage Eo to the direct current input voltage Ei becomesδ1: (Eo/Ei=δ1) and the converter operates as a voltage step-downconverter. Further, when the duty ratio δ1 is 1: (δ1=1), the ratio Eo/Eibecomes 1/(1−δ2): (Eo/Ei=1/(1−δ2), and the converter operates as avoltage step-up converter. By controlling the duty ratios of the firstand second switches 32, 35 respectively, the ratio of input and outputvoltages δ1/(1−δ2) can be set at 0 to infinity. In other words, theDC—DC converter operates as a voltage step-up and step-down convertertheoretically capable of obtaining arbitrary direct current outputvoltage Eo from arbitrary direct current input voltage Ei.

The above-mentioned control of DC—DC converter can be carried out with,for example, a DC—DC converter having a control circuit 50 shown in FIG.11( a) (See U.S. Pat. No. 4,395,675). For convenience of description,the circuit diagram shown in FIG. 11( a) is rewritten by applying thecircuit described in FIG. 9 of the U.S. Pat. No. 4,395,675 to the DC—DCconverter with the configuration as shown in FIG. 10( a). FIG. 11( b)shows operation waveforms of each section thereof. Operation of theDC—DC converter shown in FIG. 11( a) will be described below withreference to FIG. 11( b).

In FIG. 11( a), a reference voltage Vr is output from a referencevoltage source 40 of the control circuit 50 and applied to an erroramplifier 41. The error amplifier 41 compares the direct current outputvoltage Eo with the reference voltage Vr and outputs a first errorvoltage Ve1. An oscillation circuit 42 outputs an oscillation voltage Vtthat oscillates at a predetermined cycle. An offset circuit 44 receivesthe first error voltage Ve1 as an input and adds a predetermined offsetvoltage to the first error voltage Ve1 to output a second error voltageVe2.

FIG. 11( b) shows waveforms of the oscillation voltage Vt, two errorvoltages Ve1 and Ve2, and two driving signals Vg32 and Vg 35. A firstcomparator 43 compares the first error voltage Ve1 with the oscillationvoltage Vt, and outputs the driving signal Vg 35 that becomes “H” duringa period when the first error voltage Ve1 is larger than the oscillationvoltage Vt: (Ve1>Vt) (“H” indicates “high” of logical level). It isassumed that when the driving signal Vg35 is “H”, the second switch 35turns to ON state, and when it is “L”, the switch turns to OFF state(“L” indicates “low” of logical level). A second comparator 45 comparesthe second error voltage Ve2 with the oscillation voltage Vt, andoutputs the driving signal Vg 32 that becomes “H” during a period whenthe second error voltage Ve2 is larger than the oscillation voltage Vt:(Ve2>Vt). It is assumed that when the driving signal Vg32 is “H”, thefirst switch 32 turns to ON state, and when it is “L”, the switch turnsto OFF state.

In the case where the direct current input voltage Ei is sufficientlyhigher than the direct current output voltage Eo as a control target,the first error voltage Ve1 and the second error voltage Ve2 becomelower in a stable state of the direct current output voltage Eo. Duringthe period shown by A in FIG. 11( b), when the first error voltage Ve1is lower than the oscillation voltage Vt at all times, the drivingsignal Vg35 becomes “L” at all times and the second switch 35 turns toOFF state at all times. On the other hand, the driving signal Vg32 thatis set based on the comparison between the second error voltage Ve2 andthe oscillation voltage Vt drives the first switch 32 to be turned ONand OFF. In other words, operation is made as a voltage step-downconverter during the period A in FIG. 11( b).

In the case where the direct current input voltage Ei has a voltage inthe vicinity of the direct current output voltage Eo as a controltarget, as in the period shown by B in FIG. 11( b), the waveforms ofboth the first error voltage Ve1 and the second error voltage Ve2intersect the waveform of the oscillation voltage Vt. Therefore, thefirst switch 32 is driven to be turned ON and OFF by the driving signalVg32, and the second switch is driven to be turned ON and OFF by thedriving signal Vg35. In other words, the operation is made as a voltagestep-up and step-down converter during the period B in FIG. 11( b).

Furthermore, in the case where the direct current input voltage Ei islower than the direct current output voltage Eo as a control target,when the second error voltage Ve2 becomes higher than the oscillationvoltage Vt at all times as in the period shown by C in FIG. 11( b), thedriving signal Vg32 becomes “H” at all times and the first switch 32turns to ON state at all times. On the other hand, the driving signalVg35 that is set based on the comparison between the first error voltageVe1 and the oscillation voltage Vt drives the second switch 35 to turnON and OFF. In other words, the operation is made as a voltage step-upconverter during the period C in FIG. 11( b).

The ON and OFF timing of the first switch 32 and the second switch 35shown in FIG. 11( b) is different from the ON and OFF timing of thefirst switch 32 and the second switch 35 shown in FIG. 10( b). Thisdifference depends on the difference between control circuits shown inFIG. 10 and FIG. 11 in constitution and function. Combinations of ON andOFF of the first switch 32 and the second switch 35 in the DC—DCconverter are basically the following three types: both the first switch32 and the second switch 35 are in ON state; the first switch 32 is inON state and the second switch 35 is in OFF state; and both the firstswitch 32 and the second switch 35 are in OFF state. In the case wherethe first switch 32 is in the OFF state and the second switch is in theON state, the inductor 34 is short-circuited, and having no relationwith transmission of electric power between input and output, andtherefore the state of operation should be avoided. On the conditionthat any combination of the above-mentioned three types of operationstates never causes a current flowing to the inductor 34 to become zero,when the ratio of the ON time of the first switch 32 per one switchingcycle is referred as to δ1 and the ratio of the ON time of the secondswitch 35 per one switching cycle is referred as to δ2, the relation ofthe following equation (3) is established between input and outputvoltages. This also applies to the timing of the ON and OFF operation ofeach switch shown by waveforms in FIG. 10( b) as well as the timing ofON and OFF of each switch shown by waveforms in FIG. 11( b).Eo/Ei=δ1/(1−δ2)  (3)

Other examples of method for controlling a DC—DC converter capable ofcarrying out voltage step-up and step-down are disclosed in U.S. Pat.No. 5,402,060 and U.S. Pat. No. 6,166,527. Both of these compare theoscillation voltage with the error voltage and add or subtract an offsetvoltage to or from the oscillation voltage or the error voltage so thata driving signal for driving the first switch and a driving signal fordriving the second switch are formed.

The DC—DC converter of the above-mentioned U.S. Pat. No. 4,395,675requires a plurality of error voltages Ve1 and Ve2, thereby to cause theproblem of complicating the control circuit.

Further, during voltage step-up and step-down operation in which boththe first switch 32 and the second switch 35 is turned ON and OFF, therecauses the problem of increasing switching loss compared with duringvoltage step-down operation or voltage step-up operation. In order tonarrow the region where the voltage step-up and step-down operation iscarried out to solve the problem, it is necessary that the offsetvoltage to be added to the error voltage is made to a voltage in thevicinity of an amplitude of the oscillation voltage. However, when theoffset voltage is made to the voltage in the vicinity of the amplitudeof the oscillation voltage, fluctuation band of the error voltagebecomes larger in order to ensure control range in step-down voltageoperation and step-up voltage operation. For that reason, in the case oflow power supply voltage of the control circuit, there has caused aproblem of difficulties in design.

DISCLOSURE OF INVENTION

An object of the present invention is to provide a high efficiency DC—DCconverter that solves the above-mentioned problems, enables controllingthe step-up operation, the step-up and step-down operation and thestep-down operation with a simple configuration and reduces the loss.

In order to achieve the above-mentioned object, the DC—DC converteraccording to the present invention is a voltage step-up and step-downconverter comprising a step-down converter section having a firstswitch, a voltage step-up converter section having a second switch and acontrol section for turning ON and OFF the above-mentioned first switchand the above-mentioned second switch, respectively, for receiving adirect current input voltage and outputting a direct current outputvoltage to a load.

The above-mentioned control section has an error amplifying circuit forcomparing the above-mentioned direct current output voltage with apredetermined voltage and outputting an error voltage, an oscillationcircuit and a pulse width control circuit.

The above-mentioned oscillation circuit generates an oscillation voltagewhich is an oscillation voltage cyclically changing between a firstsetting voltage and a second setting voltage lower than theabove-mentioned first setting voltage, the ratio of rising time or theratio of lowering time per one cycle of the above-mentioned oscillationvoltage increases corresponding to the increase of the differencebetween the above-mentioned error voltage and the above-mentioned firstsetting voltage, when the above-mentioned error voltage is higher thanthe above-mentioned first setting voltage, and generates an oscillationvoltage in which the ratio of rising time or the ratio of lowering timeper one cycle of the above-mentioned oscillation voltage increasescorresponding to the increase of the difference between theabove-mentioned error voltage and the above-mentioned second settingvoltage, when the above-mentioned error voltage is lower than theabove-mentioned second setting voltage.

In the case where the above-mentioned error voltage is compared with theabove-mentioned oscillation voltage and the above-mentioned errorvoltage does not coincide with the above-mentioned oscillation voltage,the above-mentioned pulse width control circuit carries out control in avoltage step-down operation mode wherein the above-mentioned secondswitch is fixed at OFF state and the above-mentioned first switch isturned ON or OFF, or carries out control in a voltage step-up operationmode wherein the above-mentioned first switch is fixed at ON state andthe above-mentioned second switch is turned ON or OFF.

In the case where the above-mentioned error voltage coincides with theabove-mentioned oscillation voltage occasionally, the above-mentionedpulse width control circuit further controls the ON and OFF time of theabove-mentioned first switch and the ON and OFF time of theabove-mentioned second switch so as to carry out control in the voltagestep-up and step-down operation mode wherein both the above-mentionedfirst switch and the above-mentioned second switch are turned ON andOFF.

In the DC—DC converter of the present invention, the above-mentionederror amplifying circuit is configured so as to output the error voltagethat rises as the above-mentioned direct current output voltage is lowerthan the above-mentioned predetermined voltage and lowers as theabove-mentioned direct current output voltage is higher than theabove-mentioned predetermined voltage.

The above-mentioned oscillation circuit is configured so as to increasethe ratio of rising time per one cycle of the above-mentionedoscillation voltage as the difference between the above-mentioned errorvoltage and the above-mentioned second setting voltage increases whenthe above-mentioned error voltage is lower than the above-mentionedsecond setting voltage, and to increase the ratio of rising time per onecycle of the above-mentioned oscillation voltage as the differencebetween the above-mentioned error voltage and the above-mentioned firstsetting voltage increases when the above-mentioned error voltage ishigher than the above-mentioned first setting voltage.

The above-mentioned pulse width control circuit carries out control inthe voltage step-down operation mode wherein the above-mentioned secondswitch is fixed at OFF state, and the above-mentioned first switch isturned to OFF state in the rising period of the above-mentionedoscillation voltage and turned to ON state in the remaining period inthe case where the above-mentioned error voltage is lower than theabove-mentioned second setting voltage. The above-mentioned pulse widthcontrol circuit carries out control in the voltage step-up operationmode wherein the above-mentioned first switch is fixed at ON state, andthe above-mentioned second switch is turned to ON state in the risingperiod of the above-mentioned oscillation voltage and turned to OFFstate in the remaining period in the case where the above-mentionederror voltage is higher than the above-mentioned first setting voltage.In the case where the above-mentioned error voltage coincides with theabove-mentioned oscillation voltage occasionally, the above-mentionedpulse width control circuit further carries out control in the voltagestep-up and step-down operation mode wherein the above-mentioned firstswitch is turned to OFF state in the period during which theabove-mentioned error voltage is lower than the above-mentionedoscillation voltage in the rising period of the above-mentionedoscillation voltage and is turned to ON state in the remaining period,and the above-mentioned second switch is turned to ON state in theperiod during which the above-mentioned error voltage is higher than theabove-mentioned oscillation voltage in the rising period of theabove-mentioned oscillation voltage and is turned to OFF state in theremaining period.

In the DC—DC converter of the present invention, said oscillationcircuit has an oscillation capacitor for outputting said oscillationvoltage by being charged or discharged in response to a pulse signalhaving a predetermined cycle.

The above-mentioned oscillation circuit may be configured so as tocharge the above-mentioned oscillation capacitor when said pulse signalis input in a state wherein the above-mentioned oscillation voltage ismaintained at the above-mentioned second setting voltage, to dischargethe above-mentioned oscillation capacitor when the above-mentionedoscillation voltage reaches the first setting voltage, and to maintainthe above-mentioned oscillation voltage in the vicinity of theabove-mentioned second setting voltage without charging or dischargingthe above-mentioned oscillation capacitor when the above-mentionedoscillation voltage reaches the above-mentioned second setting voltage.

In the DC—DC converter of the present invention, the above-mentionedoscillation circuit may be configured so as to generate an oscillationvoltage in triangular wave form that rises or lowers cyclically betweenthe first setting voltage and the second setting voltage lower than theabove-mentioned first setting voltage, the oscillation voltage, thecycle of which decreases corresponding to the increase of the differencebetween the above-mentioned error voltage and the above-mentioned firstsetting voltage when the above-mentioned error voltage is higher thanthe above-mentioned first setting voltage, and the oscillation voltage,the cycle of which decreases corresponding to the increase of thedifference between the above-mentioned error voltage and theabove-mentioned second setting voltage when the above-mentioned errorvoltage is lower than the above-mentioned second setting voltage.

In the DC—DC converter of the present invention, the above-mentionederror amplifying circuit is configured so as to output the error voltagethat rises as the above-mentioned direct current output voltage becomeslower than the above-mentioned predetermined voltage, and lowers as theabove-mentioned direct current output voltage becomes higher than theabove-mentioned predetermined voltage.

The above-mentioned oscillation circuit is configured so as to increasethe ratio of rising time per one cycle of the above-mentionedoscillation voltage as the difference between the above-mentioned errorvoltage and the above-mentioned second setting voltage increases whenthe above-mentioned error voltage is lower than the above-mentionedsecond setting voltage, and to increase the ratio of rising time per onecycle of the above-mentioned oscillation voltage as the differencebetween the above-mentioned error voltage and the above-mentioned firstsetting voltage increases when the above-mentioned error voltage ishigher than the above-mentioned first setting voltage.

The above-mentioned pulse width control circuit carries out control inthe voltage step-down operation mode wherein the above-mentioned secondswitch is fixed at OFF state, and the above-mentioned first switch isturned to OFF state in the rising period of the above-mentionedoscillation voltage and turned to ON state in the remaining period inthe case where the above-mentioned error voltage is lower than theabove-mentioned second setting voltage. The above-mentioned pulse widthcontrol circuit carries out control in the voltage step-up operationmode wherein the above-mentioned first switch is fixed at ON state, andthe above-mentioned second switch is turned to ON state in the risingperiod of the above-mentioned oscillation voltage and turned to OFFstate in the remaining period in the case where the above-mentionederror voltage is higher than the above-mentioned first setting voltage.In the case where the above-mentioned error voltage coincides with theabove-mentioned oscillation voltage occasionally, the above-mentionedpulse width control circuit further carries out control in the voltagestep-up and step-down operation mode wherein the above-mentioned firstswitch is turned to OFF state in the period during which theabove-mentioned error voltage is lower than the above-mentionedoscillation voltage in the rising period of the above-mentionedoscillation voltage and is turned to ON state in the remaining period,and the above-mentioned second switch is turned to ON state in theperiod during which the above-mentioned error voltage is higher than theabove-mentioned oscillation voltage in the rising period of theabove-mentioned oscillation voltage and is turned to OFF state in theremaining period.

In the DC—DC converter of the present invention, the above-mentionedoscillation circuit is configured so as to keep the rising speed of theabove-mentioned oscillation voltage constant regardless of the change ofthe above-mentioned error voltage and to increase the lowering speed ofthe above-mentioned oscillation voltage as the above-mentioned errorvoltage becomes higher than the above-mentioned first setting voltageand as the above-mentioned error voltage becomes lower than theabove-mentioned second setting voltage.

The above-mentioned pulse width control circuit may be configured so asto turn the above-mentioned first switch to ON state and to turn theabove-mentioned second switch to OFF state in the lowering period of theabove-mentioned oscillation voltage, and to turn both theabove-mentioned first switch and the above-mentioned second switch to ONstate in the case where the above-mentioned error voltage is higher thanthe above-mentioned oscillation voltage, and to turn both theabove-mentioned first switch and the above-mentioned second switch toOFF state in the case where the above-mentioned error voltage is lowerthan the above-mentioned oscillation voltage in the rising period of theabove-mentioned oscillation voltage.

In the DC—DC converter of the present invention, the above-mentionederror amplifying circuit is configured so as to output the error voltagethat rises as the above-mentioned direct current output voltage becomeslower than the above-mentioned predetermined voltage, and lowers as theabove-mentioned direct current output voltage becomes higher than theabove-mentioned predetermined voltage.

The above-mentioned oscillation circuit is configured so as to keep thelowering speed of the above-mentioned oscillation voltage constantregardless of the change of the above-mentioned error voltage, and toincrease the rising speed of the above-mentioned oscillation voltage asthe above-mentioned error voltage becomes higher than theabove-mentioned first setting voltage and as the above-mentioned errorvoltage becomes lower than the above-mentioned second setting voltage.

The above-mentioned pulse width control circuit may be configured so asto turn the above-mentioned first switch to ON state and to turn theabove-mentioned second switch to OFF state in the rising period of theabove-mentioned oscillation voltage, and to turn both theabove-mentioned first switch and the above-mentioned second switch to ONstate in the case where the above-mentioned error voltage is higher thanthe above-mentioned oscillation voltage, and to turn both theabove-mentioned first switch and the above-mentioned second switch toOFF state in the case where the above-mentioned error voltage is lowerthan the above-mentioned oscillation voltage in the lowering period ofthe above-mentioned oscillation voltage.

In the DC—DC converter of the present invention, the above-mentionedoscillation circuit may be configured so as to extend the cycle of theabove-mentioned oscillation voltage as the difference between theabove-mentioned error voltage and a third setting voltage becomes largerin the case where the predetermined third setting voltage is comparedwith the above-mentioned error voltage and the above-mentioned errorvoltage exceeds the above-mentioned third setting voltage in thedirection of lowering the above-mentioned direct current output voltagein the above-mentioned voltage step-down operation mode.

In the DC—DC converter of the present invention, with respect to thethird setting voltage lower than the above-mentioned second settingvoltage, the above-mentioned oscillation circuit may be configured so asto extend the cycle of the above-mentioned oscillation voltage as thedifference between the above-mentioned error voltage and theabove-mentioned third setting voltage becomes larger in the case wherethe above-mentioned error voltage is lower than the above-mentionedthird setting voltage.

In the DC—DC converter of the present invention, with respect to thethird setting voltage. lower than the above-mentioned second settingvoltage, the above-mentioned oscillation circuit may be configured so asto slow the lowering speed of the above-mentioned oscillation voltage asthe difference between the above-mentioned error voltage and theabove-mentioned third setting voltage becomes larger in the case wherethe above-mentioned error voltage is lower than the above-mentionedthird setting voltage.

In the DC—DC converter of the present invention, with respect to thethird setting voltage lower than the above-mentioned second settingvoltage, the above-mentioned oscillation circuit may be configured so asto slow the rising speed of the above-mentioned oscillation voltage asthe difference between the above-mentioned error voltage and theabove-mentioned third setting voltage becomes larger in the case wherethe above-mentioned error voltage is lower than the above-mentionedthird setting voltage.

In the DC—DC converter of the present invention, the above-mentionedthird setting voltage may be set closer to the above-mentioned secondsetting voltage as the above-mentioned direct current input voltagebecomes lower.

In the DC—DC converter of the present invention, the above-mentionedcontrol section may be configured so as to have a predeterminedhysteresis characteristic in the operation of comparing theabove-mentioned error voltage with the above-mentioned first settingvoltage.

In the DC—DC converter of the present invention, the above-mentionedoscillation circuit may be configured so as to make smaller the ratio ofthe rising time per one cycle of the above-mentioned oscillation voltagewhen the above-mentioned error voltage becomes higher than theabove-mentioned first setting voltage.

In the DC—DC converter of the present invention, the above-mentionedcontrol section may be configured to have a predetermined hysteresischaracteristic in the operation of comparing the above-mentioned errorvoltage with the above-mentioned second setting voltage.

In the DC—DC converter of the present invention, the above-mentionedoscillation circuit may be configured so as to make smaller the ratio ofthe rising time per one cycle of the above-mentioned oscillation voltagewhen the above-mentioned error voltage is lower than the above-mentionedsecond setting voltage.

The DC—DC converter of the present invention is a voltage step-up andstep-down typed DC—DC converter, comprising a voltage step-downconverter section having a first switch, a voltage step-up convertersection having a second switch and a control section for turning ON andOFF the above-mentioned first switch and the above-mentioned secondswitch, respectively, for receiving a direct current input voltage andoutputting a direct current output voltage to a load.

The above-mentioned control section carries out the voltage step-up andstep-down operation in which respective driving signals that turn ON andOFF the above-mentioned first switch and the above-mentioned secondswitch are sent in the case where an oscillation voltage is comparedwith the error voltage corresponding to the above-mentioned directcurrent output voltage and the above-mentioned oscillation voltagecoincides with the above-mentioned error voltage occasionally. In thecase where the above-mentioned error voltage does not coincide with theabove-mentioned oscillation voltage, the above-mentioned controlsection, by the difference between the above-mentioned oscillationvoltage and the above-mentioned error voltage, carries out the voltagestep-down operation in which the above-mentioned second switch is fixedat OFF state and the above-mentioned first switch is turned ON and OFF,in the case where the above-mentioned error voltage does not coincidewith the above-mentioned oscillation voltage, or carries out the voltagestep-up operation in which the above-mentioned first switch is fixed atON state and the above-mentioned second switch is turned ON and OFF.

The DC—DC converter of the present invention configured as describedabove enables control from voltage step-up to voltage step-up andstep-down and further to voltage step-down by comparing one oscillationcircuit with one error voltage, whereby the configuration of the controlsection can be simplified.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1 is a circuit diagram showing configuration of a DC—DC converterin accordance with a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing configuration of a control sectionof the DC—DC converter in accordance with the first embodiment of thepresent invention.

FIGS. 3( a) to 3(c) are waveform diagrams showing operations of eachsection of the control section of the DC—DC converter in accordance withthe first embodiment of the present invention.

FIG. 4 is a circuit diagram showing configuration of a control sectionof a DC—DC converter in accordance with a second embodiment of thepresent invention.

FIGS. 5( a) to 5(c) are waveform diagrams showing operations of eachsection of the control section of the DC—DC converter in accordance withthe second embodiment of the present invention.

FIG. 6 is a circuit diagram of a control section of a DC—DC converter inaccordance with a third embodiment of the present invention.

FIG. 7 is a circuit diagram of a control section of a DC—DC converter inaccordance with a fourth embodiment of the present invention.

FIG. 8 is a circuit diagram of a control section of a DC—DC converter inaccordance with a fifth embodiment of the present invention.

FIG. 9 is a circuit diagram of a control section of a DC—DC converter inaccordance with a sixth embodiment of the present invention.

FIG. 10( a) is the circuit diagram showing configuration of theconventional DC—DC converter.

FIG. 10( b) is the waveform diagram showing operations of theconventional DC—DC converter.

FIG. 11( a) is the circuit diagram showing configuration of theconventional DC—DC converter.

FIG. 11( b) is the waveform diagram showing operations of theconventional DC—DC converter.

BEST MODE FOR CARRYING OUT THE INVENTION

Preferred embodiments of a DC—DC converter according to the presentinvention will be described below referring to the accompanying FIG. 1to FIG. 9.

FIRST EMBODIMENT

A first embodiment of the present invention will be described referringto FIG. 1 to FIG. 3.

FIG. 1 is a circuit diagram showing configuration of a DC—DC converterin accordance with the first embodiment of the present invention. InFIG. 1, the DC—DC converter 50 of the first embodiment comprises avoltage step-down converter 51 consisting of a first switch 2 formed ofa P-channel MOSFET, which is connected to a direct current input powersource 1 of a voltage Ei, a first rectifying section 3 as a diode and aninductor 4; a voltage step-up converter 52 consisting of a second switch5 formed of N-channel MOSFET and a second rectifying section 6 as adiode, having the inductor 4 in common; and an output capacitor 7. Avoltage Eo between both terminals of the output capacitor 7 is appliedto a load 8 as a direct current output voltage.

The first switch 2, the inductor 4 and the second switch 5 are connectedin series across a positive pole 1A and a negative pole 1B of the directcurrent power source 1. When both the first switch 2 and the secondswitch 5 are turned ON, the direct current input voltage Ei is appliedto the inductor 4. The first rectifying means 3, the inductor 4 and thesecond rectifying means 6 are connected in series and when both thefirst rectifying means 3 and the second rectifying means 6 are turnedON, voltage of the inductor 4 is applied to the output capacitor 7.

The control section 53 for controlling ON and OFF of the first switch 2and the second switch 5 comprises an error amplifying circuit 10, anoscillation circuit 11 and a pulse width control circuit 12. The erroramplifying circuit 10 detects the direct current output voltage Eo andoutputs an error voltage Ve. The oscillation circuit 11 outputs anoscillation voltage Vt. The pulse width control circuit 12 receivesinputs of the error voltage Ve and the oscillation voltage Vt andoutputs a driving voltage Vg2 for driving the first switch 2 to beturned ON and OFF and a driving voltage Vg5 for driving the secondswitch 5 to be turned ON and OFF.

FIG. 2 is a detailed circuit diagram of the error amplifying circuit 10,the oscillation circuit 11 and the pulse width control circuit 12.

In FIG. 2, the error amplifying circuit 10 comprises a reference voltagesource 100, two resistors 101 and 102 connected in series for dividingthe direct current output voltage Eo and an error amplifier 103 forcomparing a voltage Er of the reference voltage source 100 with detectedvoltage, amplifying the error of comparison result and outputting theerror signal Ve.

The oscillation circuit 11 comprises an oscillation capacitor 110 havinga capacitance C and a constant current circuit 111, and comprises amirror circuit consisting of an PNP transistor 112 and an PNP transistor113 for charging the oscillation capacitor 110 by a constant current I1flowing through a constant current circuit 111. Moreover, a seriescircuit of a resistor 114, a diode 115 and a resistor 116 provided fordividing the direct current input voltage Ei and outputting a firstsetting voltage E1 and a second setting voltage E2. The circuit furthercomprises a current mirror circuit consisting of an NPN transistor 117and an NPN transistor 118 for discharging the oscillation capacitor 110,and an NPN transistor 130, a base terminal of which is connected to anoutput point of the first setting voltage E1. A resistor 131 isconnected between the emitter terminal of the NPN transistor 130 and theoutput terminal of the error amplifier 103.

A current mirror circuit consisting of a PNP transistor 132 and a PNPtransistor 133 is configured so that the current flowing through theresistor 131 is supplied to a current mirror circuit consisting of anNPN transistor 117 and an NPN transistor 118. The second setting voltageE2 is applied to the base terminal of a PNP transistor 134, and thecollector terminal thereof is connected to the base terminal of the NPNtransistor 117. A resistor 135 is connected between the emitter terminalof the PNP transistor 134 and the output terminal of the error amplifier103. A comparator 136 compares the first setting voltage E1 with thevoltage Vt of the oscillation capacitor 110. A comparator 137 comparesthe second setting voltage E2 with the voltage Vt of the oscillationcapacitor 110. The output of the comparator 136 is input to an NORcircuit 138, and an NOR circuit 139 and the NOR circuit 138 form aflip-flop.

A clock signal source 140 outputs a one shot pulse of cycle T to the NORcircuit 139. A P-channel MOSFET 141 is driven by an output Vx of the NORcircuit 138, and short-circuits across the emitter and the base of thecurrent mirror circuit consisting of the PNP transistor 112 and the PNPtransistor 113. The output of an NOR circuit 142 to which an output Vxof the NOR circuit 138 and the output of the comparator 137 are input isapplied to the gate of an N-channel MOSFET 143 and drives it.

The oscillation capacitor 110 is discharged via the N-channel MOSFET 143and a resistor 144 connected thereto. An N-channel MOSFET 145 which isdriven by the application of the output of the NOR circuit 139 to thegate short-circuits across the emitter and the base of the currentmirror circuit consisting of the PNP transistor 117 and the PNPtransistor 118.

The pulse width control circuit 12 comprises a comparator 120 forcomparing the output voltage Ve of the error amplifier 103 with thevoltage Vt of the oscillation capacitor 110. An output Vy of thecomparator 120 and the output of the NOR circuit 139 are input to an ORcircuit 121. The output Vy of the comparator 120 and the output Vx ofthe NOR circuit 138 are input to an AND circuit 122. The output of theOR circuit 121 is input to the first switch 2 via an inverter 123. Itbecomes a driving voltage Vg2 of the first switch 2. The output of theAND circuit 122 is a driving voltage Vg5 of the second switch 5.

Operation of the DC—DC converter in accordance with the first embodimentconfigured as mentioned above will be described below.

The first switch 2 and the second switch 5 carry out the ON and OFFoperation at the same switching cycle T by means of the control section53. The duty ratios which are ratios of respective ON times of the firstswitch 2 and the second switch 5 in one switching cycle are designatedas δ1 and δ2, respectively. It is assumed that in a period when thesecond switch 5 is in the ON state, the first switch 2 is also in the ONstate, and the duty ratio δ1 is larger than the duty ratio δ2: (δ1>δ2).For convenience of description, the forward voltage drops of the firstrectifying section and the second rectifying section in the ON state areignored.

First, when both the first switch 2 and the second switch 5 are in theON state, the voltage Ei of the direct current input power source 1 isapplied to the inductor 4. The application period is represented by theproduct of the duty ratio δ2 by the cycle T: (δ2·T). In this period, acurrent flows from the direct current input power source 1 to theinductor 4, and magnetic energy is stored therein.

Next, when both the first switch 2 and the second switch 5 are in theOFF state, the first rectifying section 3 and the second rectifyingsection 6 turn to ON state, and the direct current output voltage Eo isapplied to the inductor 4 in the reverse direction. The applicationperiod is represented by the value obtained by subtracting the productof the duty ratio δ1 by the cycle T from the cycle T: (T−δ1·T), and acurrent flows from the inductor 4 to the output capacitor 7, and thestored magnetic energy is released.

Finally, when the first switch 2 is in the ON state and the secondswitch 5 is in the OFF state, the second rectifying section 6 turns toON state, and the voltage of difference between the direct current inputvoltage Ei and the direct current output voltage Eo: (Ei−Eo) is appliedto the inductor 4. This period is represented by the equation(δ1·T−δ2·T) and a current flows from the direct current input powersource 1 to the output capacitor 7 via the inductor 4.

As described above, by repeating the operation of storage and release ofmagnetic energy, electric power is supplied from the output capacitor 7to the load 8. In a stable operation state wherein the storage and therelease of magnetic energy at the inductor 4 balance, since the sum ofthe product of applied voltages and times of application to the inductor4 is zero, the below-mentioned equation (4) is established.Ei·δ2·T+(Ei−Eo)(δ1·T−δ2·T)−Eo(T−δ1·T)=0  (4)

By arranging the above-mentioned equation (4), a conversioncharacteristic equation represented by the following equation (5) isobtained.Eo/Ei=δ1/(1−δ2)  (5)

As understood from the above-mentioned conversion characteristicequation (5), by controlling the duty ratios δ1 and δ2, the arbitrarydirect current output voltage Eo can be theoretically obtained from thearbitrary direct current input voltage Ei, enabling the DC—DC converterto operate as a step-up and step-down converter.

When the duty ratio δ2 is zero: (δ2=0), in which the second switch 5 isin the OFF state at all times, the operation enters the voltagestep-down mode wherein the converter operates as a voltage step-downconverter as represented by the following equation (6).Eo/Ei=δ1  (6)

When the duty ratio δ1 is equal to 1:(δ1=1), in which the first switch 2is in the ON state at all times, the operation enters the voltagestep-up mode wherein the converter operates as a voltage step-upconverter as represented by the following equation (7).Eo/Ei=1/(1−δ2)  (7)

FIGS. 3( a) to 3(c) are waveform diagrams of each section of the controlsection 53 shown in FIG. 2. FIGS. 3( a) to 3(c) show waveforms of thepulse output Vc of the clock signal source 140, the oscillation voltageVt of the oscillation capacitor 110, the error voltage Ve of the erroramplifying circuit 10, the output Vx of the NOR circuit 138, the outputVy of the comparator 120 in the pulse width control circuit 12, theoutput V121 of the OR circuit 121 and the driving voltage Vg5 for thesecond switch 5. The reason why FIG. 3 shows the output V121 of the ORcircuit 121 which is a turnover voltage of the driving voltage Vg2 forthe first switch 2, not the driving voltage Vg2 is as follows.

Since the first switch 2 is a P-channel MOSFET, it turns to ON statewhen the driving voltage Vg2 applied to the gate is “L” (“low” oflogical level) and turns to OFF state when it is “H” (“high” of logicallevel). Therefore, the waveform representing ON and OFF states representan opposite meaning to waveform of an ordinary switch that turns OFF at“L” and turns ON at “H”, whereby confusion is liable to cause. In FIG.2, logical NOR of the output Vy of the comparator 120 and the output ofthe NOR circuit 139 should be set to the driving voltage Vg2, but inorder to facilitate understanding, it is configured by the OR circuitand the inverter 123, and the output V121 of the OR circuit 121 is shownin FIG. 3. In other words, in FIG. 3, to be easily understandable, thefirst switch turns to ON state at “H” and turns to OFF state at “L” byrepresenting the output V121 of the OR circuit 121. FIG. 3( a) shows thecase wherein the oscillation voltage Vt is larger than the error voltageVe, FIG. 3( b) shows the case wherein the waveforms of the oscillationvoltage Vt and the error voltage Ve intersect with each other, that is,coincide with each other occasionally, and FIG. 3( c) shows the casewherein the oscillation voltage Vt is smaller than the error voltage Ve.

Operation of the control section 53 will be described with reference toFIG. 2 and FIG. 3. For convenience of description, it is assumed thatthe forward voltage drop of the diode, that is, the base-emitter voltageof the NPN transistor in the ON state and the base-emitter voltage ofthe PNP transistor in the ON state are equal, and this value isrepresented by a voltage Vd. The voltage Vd is equal to the differencebetween the first setting voltage E1 and the second setting voltage E2.

The error voltage Ve output from the error amplifying circuit 10 lowerswhen the voltage detected by dividing the direct current output voltageEo by the resistor 101 and the resistor 102 is higher than the referencevoltage Er of the reference voltage source 100, and rises when thevoltage is lower the reference voltage Er. In other words, the errorvoltage Ve lowers when the direct current input voltage Ei becomeshigher or the direct current output voltage Eo rises owing to decreasein the load 8. On the contrary, the error voltage Ve rises when thedirect current input voltage Ei becomes lower or the direct currentoutput voltage Eo lowers owing to increase in the load 8. FIG. 3( a)shows the state wherein the error voltage Ve is lower than theoscillation voltage Vt, and the direct current input voltage Ei ishigher than the direct current output voltage Eo. FIG. 3( b) shows thestate wherein waveforms of the error voltage Ve and the oscillationvoltage Vt cross with each other, and the direct current input voltageEi is close to the direct current output voltage Eo. The FIG. 3( c)shows the state wherein the error voltage Ve is higher than theoscillation voltage Vt and the direct current input voltage Ei is lowerthan the oscillation voltage Vt.

The oscillation capacitor 110 of the oscillation circuit 11 is chargedor discharged between the first setting voltage E1 and the secondsetting voltage E2: (E2<E1), and outputs the oscillation voltage Vt.This charge period starts at receiving the pulse signal Vc from theclock signal source 140.

First, the NOR circuit 139 outputs “L” and the output Vx of the NORcircuit 138 constituting a flip-flop in combination with the NOR circuit139 turns to “H”. For this reason, the FET 141 turns to OFF state, andthe current I1 of the constant current source 111 flows to theoscillation capacitor 110 through the current mirror circuit consistingof the PNP transistor 112 and the PNP transistor 113, whereby theoscillation capacitor 110 is charged. Since the FET 143 is in the OFFstate, discharge by the resistor 144 is not performed. However, sincethe FET 145 is in the OFF state, discharge by the current mirror circuitconsisting of the NPN transistor 117 and the NPN transistor 118 isperformed. The discharge current by the current mirror circuitconsisting of the NPN transistor 117 and the NPN transistor 118 isdetermined depending on the error voltage Ve.

As shown in FIG. 3( b), in the case where the error voltage Ve isbetween the first setting voltage E1 and the second setting voltage E2,both the NPN transistor 130 and the PNP transistor 134 turn to OFFstate. Therefore, there is no current discharged from the oscillationcapacitor 110 through the current mirror circuit consisting of the NPNtransistor 117 and the NPN transistor 118, and the oscillation capacitor110 is charged by the constant current I1. Therefore, charge speed ofthe oscillation capacitor 110, that is, rising speed of the oscillationvoltage Vt is constant.

As shown in FIG. 3( a), when the error voltage Ve is lower than thesecond setting voltage E2, the PNP transistor 134 turns to OFF state,and the NPN transistor 130 turns to ON state, whereby a current flows tothe resistor 131. The voltage obtained by subtracting the voltage Vd andthe error voltage Ve from the first setting voltage E1: (E1−Vd−Ve) isapplied to the resistor 131. Since the second setting voltage E2 isequal to the difference between the first setting voltage E1 and thevoltage Vd: (E2=E1−Vd), when it is assumed that the value of resistanceof the resistor 131 is R131, the current flowing through the resistor131 is calculated by the equation (E2−Ve)/R131. This current flows fromthe oscillation capacitor 110 through the current mirror circuitincluding the PNP transistor 132 and the PNP transistor 133 as well asthe current mirror circuit including the NPN transistor 117 and the NPNtransistor 118, whereby the oscillation capacitor 110 is discharged.However, this current is set as not to be larger than the constantcurrent I1 even when the voltage Ve becomes lowest. Therefore, theoscillation capacitor 110 is charged by the current I131 represented bythe following equation (8).I131=I1−(E2−Ve)/R131  (8)

As the error voltage Ve becomes lower than the second setting voltageE2, the charge current I131 becomes smaller and a charge speed of theoscillation capacitor 110, that is, rising speed of the oscillationvoltage Vt becomes slower.

As shown in FIG. 3( c), in the case where the error voltage Ve is higherthan the first setting voltage E1, the NPN transistor 130 turns to OFFstate and the PNP transistor 134 turns to ON state, whereby a currentflows through the resistor 135. The voltage represented by the equation(Ve−(E2+Vd)) is applied to the resistor 135. Since the first settingvoltage E1 is the sum of the second setting voltage E2 and the voltageVd: (E1=E2+Vd), when it is assumed that the value of resistance of theresistor 135 is R135, the current flowing through the resistor 135 isrepresented by the equation (Ve−E1)/R135. This current flows through thecurrent mirror circuit including the NPN transistor 117 and the NPNtransistor 118, whereby the oscillation capacitor 110 is discharged.However, this current is set as not to be larger than the constantcurrent I1 even when the voltage Ve becomes highest. Therefore, theoscillation capacitor 110 is charged at a current I135 represented bythe following equation (9).I135=I1−(Ve−E1)/R135  (9)

As the error voltage Ve becomes higher than the first setting voltageE1, the charge current I135 becomes smaller and charge speed of theoscillation capacitor 110, that is, rising speed of the oscillationvoltage Vt becomes slower.

Charge of the oscillation voltage 110 proceeds, and when the oscillationvoltage Vt reaches the first setting voltage E1, the output of thecomparator 136 turns “H” and the output Vx of the NOR circuit 138 of theflip-flop turns “L”. At the same time, the output Vx of the NOR circuit139 turns “H”. When the output Vx is “L”, the FET 141 turns to ON stateand the PNP transistor 113 turns to OFF state, thereby stopping thecharge current to the oscillation capacitor 110. Since the output of theNOR circuit 142 is “H”, the FET 143 turns to ON state and theoscillation capacitor 110 is discharged by the resistor 144. The FET 145which receives the output of “H” from the NOR circuit 139, turns to ONstate. Consequently, the NPN transistor 118 turns to OFF state anddischarge of the oscillation capacitor 110 through the NPN transistor118 is stopped. Therefore, the oscillation capacitor 110 is dischargedvia only the resistor 144, and the oscillation voltage Vt decreases.

When discharge of the oscillation voltage 110 proceeds and when theoscillation voltage Vt reaches the second setting voltage E2, the outputof the comparator 137 turns “H” and the output Vx of the NOR circuit 142turns “L”. Hence, the FET 143 turns to OFF state and discharge of theoscillation capacitor 110 is stopped. Since the oscillation capacitor110 is not charged nor discharged in this state, the oscillation voltageVt is maintained at the voltage slightly lower than the second settingvoltage E2. In this state, the input of a next pulse signal from theclock signal source 140 is waited. When the pulse signal is input fromthe clock signal source 140, the output of the flip-flop formed of theNOR circuit 138 and the NOR circuit 139 is inverted. Consequently,charge is restarted.

As mentioned above, the oscillation capacitor 110 is charged ordischarged between the first setting voltage E1 and the second settingvoltage E2, and outputs the oscillation voltage Vt. In the firstembodiment, since the potential difference between the first settingvoltage E1 and the second setting voltage E2 is Vd, the rising period Tcof the oscillation voltage Vt is represented by the following equations(10) to (12).

When Ve<E2,Tc=C·R131·Vd/(E2−Ve)  (10)

When E2≦Ve≦E1,Tc=C·Vd/I1  (11)

When Ve>E1,Tc=C·R135·Vd/(Ve−E1)  (12)

In the pulse width control circuit 12, the output V121 of logical sumobtained by inputting the output Vy of the comparator 120 and the outputof the NOR circuit 139 to the OR circuit 121 is input to the inverter123 and inverted, whereby the driving voltage Vg2 can be obtained asoutput. The driving voltage Vg2 turns “H” in the rising period of theoscillation voltage Vt during which the output Vx is “H”, and in aperiod during which the voltage Ve is smaller than the oscillationvoltage Vt: (Ve<Vt) and the output Vy is “L”. In other words, the firstswitch 2 turns to OFF state only in the above-mentioned period (Ve<Vt)in the rising period of the oscillation voltage Vt.

On the other hand, the driving voltage Vg5 as logical product can beobtained by inputting the output Vy of the comparator 120 and the outputVx of the NOR circuit 138 to the AND circuit 122. The driving voltageVg5 turns “H” in the rising period of the oscillation voltage Vt duringwhich the output Vx is “H” and in a period during which the voltage Veis higher than the oscillation voltage Vt: (Ve>Vt) and output thereof.Vy is “H”. In other words, the second switch 5 turns to ON state only inthe above-mentioned period (Ve>Vt) in the rising period of theoscillation voltage Vt.

As shown in FIG. 3( a) in the case where the direct current inputvoltage Ei is higher than the direct current output voltage Eo, and theerror voltage Ve is lower than the oscillation voltage Vt, the output Vyof the comparator 120 is “L” at all times, and therefore the drivingvoltage Vg5 is “L” at all times and the second switch 5 is in the OFFstate at all times. On the other hand, since the output V121 of the ORcircuit 121, that is, the inverted voltage of the driving voltage Vg2becomes “L” in the rising period of the oscillation voltage Vt, thefirst switch 2 is in the OFF state in the rising period of theoscillation voltage Vt and in the ON state in the remaining period. TheOFF period (1−δ1)T during which the first switch 2 is in the OFF stateis represented by the following equation (13).(1−δ1)T=Tc=C·R131·Vd/(E2−Ve)  (13)

In this case, the DC—DC converter in accordance with the firstembodiment enters the voltage step-down operation mode wherein itoperates with the duty ratio δ1 represented by the following equation(14).δ1=1−C·R131·Vd/(E2−Ve)/T  (14)

The lower the error voltage Ve becomes, the smaller the duty ratio δ1 ofthe first switch 2 becomes. By controlling so that the error voltage Velowers and the duty ratio δ1 becomes smaller as the direct current inputvoltage Ei becomes higher, the direct current output voltage Eo can bestabilized.

As shown in FIG. 3( b), in the case where the value of the directcurrent input voltage Ei is close to that of the direct current outputvoltage Eo and the waveform of the error voltage Ve intersects that ofthe oscillation voltage Vt, that is, the error voltage Ve coincides withthe oscillation voltage Vt occasionally, the second switch 5 turns to ONstate only in the period during which the error voltage Ve is largerthan the oscillation voltage Vt: (Ve>Vt) in the rising period Tc of theoscillation voltage Vt. The first switch 2 turns to OFF state only inthe period during which the error voltage Ve is smaller than theoscillation voltage Vt: (Ve<Vt) in the rising period Tc of theoscillation voltage Vt. In the rising period Tc of the oscillationvoltage Vt, the period in (Ve>Vt) is represented by the equationC(Ve−E2)/I1, and the period in Ve<Vt is represented by the equationC(E1−Ve)/I1. Therefore, the operation mode of the DC—DC converter inaccordance with the first embodiment is the voltage step-up andstep-down operation mode wherein the first switch 2 carries out the ONand OFF operation at the duty ratio δ1 represented by the followingequation (15), and the second switch 5 carries out the ON and OFFoperation at the duty ratio δ2 represented by the following equation(16).δ1=1−C(E1−Ve)/I1/T  (15)δ2=C(Ve−E2)/T  (16)

The smaller the error voltage Ve lowers, the higher the direct currentinput voltage Ei becomes, and the duty ratio δ1 of the first switch 2becomes smaller, and the duty ratio δ2 of the second switch 5 becomessmaller. Hence, the direct current output voltage Eo can be controlledso, as to stabilize.

As shown in FIG. 3( c), in the case where the direct current inputvoltage Ei is lower than the direct current output voltage Eo and theerror voltage Ve is higher than the oscillation voltage Vt, the outputVy of the comparator 120 is “H” at all times. Therefore, the output V121of the OR circuit 121, that is, the inverted voltage of the drivingvoltage Vg2 is “H” at all times, and the first switch 2 is in the ONstate at all times. Since the driving voltage Vg5 is “H” in the risingperiod of the oscillation voltage Vt, the second switch 5 turns to ONstate in the rising period of the oscillation voltage Vt, and turns toOFF state in the remaining period. The ON period δ2·T during which thesecond switch 5 turns to ON state is represented by the followingequation (17).δ2·T=Tc=C·R135·Vd/(Ve−E1)  (17)

In this case, the DC—DC converter in accordance with the firstembodiment enters the voltage step-up operation mode wherein it operatesat the duty ratio δ2 represented by the following equation (18).δ2=C·R135·Vd/(Ve−E1)/T  (18)

The duty ratio δ2 that decides the ON period of the second switch 5becomes larger as the error voltage Ve rises. As the direct currentinput voltage Ei lowers, the error voltage Ve rises, and the duty ratioδ2 becomes larger. Hence, the direct current output voltage Eo can becontrolled so as to stabilize.

As described above, by comparing one oscillation voltage Vt with oneerror voltage, the DC—DC converter in accordance with the firstembodiment transmits two driving signals that carry out the ON and OFFoperation of the first switch and the second switch. Hence, it becomespossible to control the voltage step-down operation, the voltage step-upor step-down operation, and the voltage step-up operation.

In the above-mentioned first embodiment, the description is made as tothe case wherein the error voltage Ve of the error amplifying circuit 11lowers when the direct current output voltage Eo rises, and rises whenthe direct current output voltage Eo lowers conversely. However, thepresent invention is not limited to this operation, and the reverseoperation of the above-mentioned operation can be performed by reversingthe driving signal Vg2 and the driving signal Vg5. Also in this case, anoperation similar to the DC—DC converter in accordance with the firstembodiment of the present invention is carried out.

The DC—DC converter in accordance with the first embodiment of thepresent invention has been configured so that the first setting voltageEl and the second setting voltage E2 are obtained by voltage-dividingthe direct current input voltage Ei by the resistor 114, the diode 115and the resistor 116. This configuration in the first embodiment isadopted because the voltages for the mirror circuits can be obtained onthe high-potential side and the low-potential side, and because theamplitude of the oscillation voltage Vt can be fixed. However, theeffect of the present invention remains unchanged even if the firstsetting voltage E1 and the second setting voltage E2 are set by usingthe respective reference voltage sources and the like, and the presentinvention is not limited to the voltage dividing method.

In the method for controlling the DC—DC converter in accordance with thefirst embodiment of the present invention, the rising period of theoscillation voltage Vt is made longer as the error voltage Ve is higherthan the first setting voltage E1 or the error voltage Ve is lower thanthe second setting voltage E2. On the other hand, the rising period ofthe oscillation voltage Vt is fixed at the minimum value when the errorvoltage Ve is equal to the second setting voltage E2 or more and isequal to the first setting voltage E1 or less (E2≦Ve≦E1). However, thepresent invention is not limited to the above-mentioned control method.For example, the present invention includes the configuration whereinanother setting voltage Ex having a voltage between the first settingvoltage E1 and when the second setting voltage E2 is set, the errorvoltage Ve is compared with the setting voltage Ex and the error voltageVe is equal to the setting voltage Ex: (Ve=Ex), the rising period of theoscillation voltage Vt is minimized, and the rising period of theoscillation voltage Vt is made longer as the potential differencebetween the error voltage Ve and the setting voltage Ex becomes larger.

In the DC—DC converter in accordance with the first embodiment of thepresent invention, although the timing of charging the oscillationcapacitor 110 is regulated by the pulse signal from the clock signalsource 140, the clock signal source 140 may be provided outside theDC—DC converter in accordance with the first embodiment of the presentinvention. In other words, the DC—DC converter in accordance with thefirst embodiment of the present invention can be configured so as tohave a receiving means for receiving an external signal, and operate asa DC—DC converter of external-synchronization-type that operates insynchronism with the external signal. Incidentally, in the DC—DCconverter in accordance with the first embodiment, although the risingperiod of the oscillation voltage Vt is changed by the error voltage Veand is controlled, it may be also controlled by changing the loweringperiod by the error voltage Ve. This also is applicable to a thirdembodiment to a sixth embodiment.

SECOND EMBODIMENT

A DC—DC converter in accordance with a second embodiment of the presentinvention will be described referring to FIG. 4 and FIG. 5.

FIG. 4 is a circuit diagram showing the configuration of a controlsection 53A of the DC—DC converter in accordance with the secondembodiment of the present invention. The control section 53A isincorporated into the converter section 50 in place of the controlsection 53 shown in FIG. 1 to constitute the DC—DC converter inaccordance with the second embodiment. In the control section 53A of theDC—DC converter in accordance with the second embodiment, the erroramplifying circuit 10 and the pulse width control circuit 12 are thesame as those of the control section 53 of the DC—DC converter inaccordance with the first embodiment. Further, as will be described indetail below, an oscillation circuit 11A is the same as theabove-mentioned oscillation circuit 11 of the control section 53 exceptfor a part. In FIG. 4, the same reference numerals are applied toelements having the same function and configuration as those of thefirst embodiment and the descriptions thereof are omitted.

A constant current circuit 146 for supplying a constant current I2 isprovided in the oscillation circuit 11A of the control section 53A ofthe DC—DC converter in accordance with the second embodiment shown inFIG. 4. The constant current circuit 146 supplies a current to thecurrent mirror circuit including the NPN transistor 117 and the NPNtransistor 118. The output of the comparator 137 in place of the clocksignal source 140 in FIG. 2 is input to the NOR circuit 139 that forms aflip-flop. The output Vx of the NOR circuit 138 is input to the gate ofthe N-channel MOSFET 145 connected across the base and the emitter ofthe NPN transistor 117. The NOR circuit 142, N-channel MOSFET 143 andresistor 144 in FIG. 2 are not provided in the oscillation circuit 11Ain FIG. 4. Other configuration of the control section 53A is the same asthat of the above-mentioned control section 53. The DC—DC converter inaccordance with the second embodiment thus configured will be describedreferring to FIG. 1 and FIG. 4. The DC—DC converter has a conversioncharacteristic represented by the following equation (19).Eo/Ei=δ1/(1−δ2)  (19)

In the case where the duty ratio δ2 is zero: (δ2=0), in which the secondswitch 5 is in the OFF state at all times, the equation (19) turns intothe following equation (20) and the operation enters the voltagestep-down mode wherein the converter operates as a voltage step-downconverter.Eo/Ei=δ1  (20)

Furthermore, in the case where the duty ratio δ1 is 1: δ1=1), in whichthe first switch 2 is in the ON state at all times, the equation (19)turns into the following equation (21) and the operation enters thevoltage step-up mode wherein the converter operates as a voltage step-upconverter.Eo/Ei=1/(1−δ2)  (21)

As mentioned above, a conversion characteristic equation of input andoutput in the second embodiment is the same as that in theabove-mentioned first embodiment.

FIGS. 5( a) to 5(c) are waveform diagrams of each section of the controlsection 53A shown in FIG. 4. FIGS. 5( a) to 5(c) show each waveform ofthe oscillation voltage Vt, the error voltage Ve, the output Vx of theNOR circuit 138, the output Vy of the comparator 120, the output V121 ofthe OR circuit 121, that is, the inverted voltage of the driving voltageVg2 of the first switch 2 and the driving voltage Vg5 of the secondswitch 5. FIG. 5( a) shows the case wherein the oscillation voltage Vtis larger than the error voltage Ve, 5(b) shows the case wherein thewaveform of the oscillation voltage-Vt crosses that of the error voltageVe, and 5(c) shows the case wherein the oscillation voltage Vt issmaller than the error voltage Ve.

Operation of the control section 53A shown in FIG. 4 will be describedreferring to FIGS. 5( a) to 5(c).

The error voltage Ve output from the error amplifying circuit 10 issimilar to that of the DC—DC converter in accordance with the firstembodiment, and lowers when the direct current input voltage Ei becomeshigher or when the load 8 becomes lighter and the direct current outputvoltage Eo rises. Conversely, the error voltage Ve rises when the directcurrent input voltage Ei becomes lower or when the load 8 becomesheavier and the direct current output voltage Eo lowers. FIG. 5( a)shows the state wherein the direct current input voltage Ei is higherthan the direct current output voltage Eo and the error voltage Ve islower than the oscillation voltage Vt. FIG. 5( b) shows the statewherein the direct current input voltage Ei is close to the directcurrent output voltage Eo and the waveform of the error voltage Vecrosses that of the oscillation voltage Vt. FIG. 5( c) shows the statewherein the direct current input voltage Ei is lower than the directcurrent output voltage Eo and the error voltage Ve is higher than theoscillation voltage Vt.

The oscillation capacitor 110 of the oscillation circuit 11A is chargedor discharged between the first setting voltage E1 and the secondsetting voltage E2: (E2<E1) and outputs the oscillation voltage Vt. Thisoscillation voltage Vt rises by supplying the current I1 of the constantcurrent source 111 to charge the oscillation capacitor 110 through thecurrent mirror circuit including the PNP transistor 112 and the PNPtransistor 113, and the rising speed is constant. During this chargeperiod, both outputs of the comparator 136 and the comparator 137 are“L”, and the outputs of the flip-flop including the NOR circuits 138 and139 to which two respective output signals of “L” are input are “H” inthe output Vx of the NOR circuit 138, and “L” in the output of the NORcircuit 139. The signal Vx of “H” makes the FET 145 turn to ON state andthe NPN transistor 118 that discharges the oscillation capacitor 110turn to OFF state. It is assumed that the electrostatic capacitance ofthe oscillation capacitor 110 is C, the charge period, that is, therising period Tc of the oscillation voltage Vt is represented by thefollowing equation (22).Tc=C(E1−E2)/I1=C·Vd/I1  (22)

When the voltage Vt of the oscillation capacitor 110 reaches the firstsetting voltage E1, the output of the comparator 136 turns to “H” andthe output Vx of the NOR circuit 138 which forms the flip-flop, turns to“L” and the output of the NOR circuit is inverted to “H”. The output Vxof “L” turns the FET 141 to ON state so that the PNP transistor 113turns to OFF state, and turns the FET 145 to OFF state so that the NPNtransistor 118 turns to ON state. Hence, the oscillation capacitor 110is discharged. The discharge current flowing through the NPN transistor118 that forms the current mirror circuit in combination with the NPNtransistor 117 is the sum of the constant current I2 and the collectorcurrent of the PNP transistor 133 and the PNP transistor 134. Thelowering period of the oscillation voltage Vt is set depending on theerror voltage Ve as follows.

Firstly, in the case where the error voltage Ve is lower than the secondsetting voltage E2 as shown in FIG. 5( a), the voltage obtained bysubtracting the voltage Vd and the error voltage Ve from the firstsetting voltage E1: (E1−Vd−Ve) is applied to the resistor 131. Since thevoltage obtained by subtracting the voltage Vd from the first settingvoltage E1 is equal to the second setting voltage E2: (E1−Vd=E2), whenit is assumed that the value of resistance of the resistor 131 is R131,the current flowing through the resistor 131 from the NPN transistor 130has a value represented by equation (E2−Ve)/R131. This current issupplied through the current mirror circuit formed of the PNP transistor132 and the PNP transistor 133 to the base terminal of the NPNtransistor 117, and in conjunction with the constant current I2, forms adischarge current for discharging the oscillation capacitor 110. In thiscase, the discharge period, that is, the lowering period Td1 of theoscillation voltage Vt is represented by the following equation (23) andbecomes shorter as the voltage obtained by subtracting the voltage Vefrom the second setting voltage E2: (E2−Ve) becomes larger.Td1=C·Vd/{I2+(E2−Ve)/R131}  (23)

Secondly, in the case where the voltage Ve is equal to the secondsetting voltage E2 or more and is equal to the first setting voltage orless (E2≦Ve≦E1), both the NPN transistor 130 and the PNP transistor 134turn to OFF state. Therefore, the current for discharging theoscillation capacitor 110 is I2 only. In this case, the dischargeperiod, that is, the lowering period Td2 of the oscillation voltage Vtis represented by the following equation (24) and becomes independent ofthe error voltage Ve.Td2=C·Vd/I2  (24)

Furthermore, as shown in FIG. 5( c), in the case where the error voltageVe is higher than the first setting voltage E1: (Ve>E1), the voltagerepresented by the equation (Ve−(E2+Vd)) is applied to the resistor 135.Since the sum of the second setting voltage E2 and the voltage Vd isequal to the first setting voltage E1: (E2+Vd=E1), when it is assumedthat the value of resistance of the resistor 135 is R135, the currentflowing through the resistor 135 from the PNP transistor 134 has a valuerepresented by the equation (Ve−E1)/R135. This current is supplied tothe base terminal of the transistor 117, and in conjunction with theconstant current I2, forms the current for discharging the oscillationcapacitor 110. In this case, the discharge period, that is, the loweringperiod Td3 of the oscillation voltage Vt is represented by the followingequation (25) and becomes shorter as the voltage obtained by subtractingthe first setting voltage E1 from the voltage (Ve−E1) becomes larger.Td3=C·Vd/{I2+(Ve−E1)/R135}  (25)

Operation of the pulse width control circuit 12 is similar to that ofthe first embodiment, and the first switch 2 turns to OFF state only inthe period when the voltage Ve is smaller than the oscillation voltageVt: (Ve<Vt) in the rising period of the oscillation voltage Vt. Further,the second switch 5 turns to ON state only in the period when thevoltage Ve is larger than the oscillation voltage Vt: (Ve>Vt) in therising period of the oscillation voltage Vt.

in the case where the direct current input voltage Ei is higher than thedirect current output voltage and the error voltage Ve is lower than theoscillation voltage Vt as shown in FIG. 5( a), the output Vy of thecomparator 120 is “L” at all times, and therefore, the driving voltageVg5 is “L” at all times and the second switch 5 is in the OFF state atall times. On the other hand, the output V121 of the OR circuit 121 asan inverted voltage of the driving voltage Vg2 turns to “L” in therising period of the oscillation voltage Vt, and turns to “H” in thelowering period of the oscillation voltage Vt. Therefore, the firstswitch 2 turns to OFF state in the rising period Tc of the oscillationvoltage Vt and turns to ON state in the lowering period Td1. Hence, theDC—DC converter in accordance with the second embodiment enters thevoltage step-down mode wherein the first switch 2 carries out the ON andOFF operation in the ON period δ1·T(=Td1) and the OFF period(1−δ1)T(=Tc). At this time, the lowering period Td1 as the ON period ofthe first switch 2 becomes shorter as the error voltage Ve becomes loweras mentioned above. As the direct current input voltage Ei becomeshigher, the error voltage Ve lowers and the ON period δ1·T of the firstswitch 2 becomes shorter, whereby the direct current output voltage Eocan be controlled so as to be stabilized.

In the case where the direct current input voltage Ei is close to thedirect current output voltage Eo and the waveform of the error voltageVe crosses that of the oscillation voltage Vt as shown in FIG. 5( b),the second switch 5 turns to ON state only when the the voltage Ve islarger than the oscillation voltage Vt: (Ve>Vt) in the rising period Tcof the oscillation voltage Vt. Furthermore, The first switch 2 turns toOFF state only when the voltage Ve is smaller than the oscillationvoltage Vt: (Ve<Vt) in the rising period Tc of the oscillation voltageVt. The period during which the voltage Ve is larger than theoscillation voltage Vt: (Ve>Vt) in the rising period Tc of theoscillation voltage Vt is represented by the following equation (26).Tc(Ve−E2)/(E1−E2)=Tc(Ve−E2)/Vd  (26)

Furthermore, the period during which the voltage Ve is smaller than theoscillation voltage Vt: (Ve<Vt) is represented by the following equation(27).Tc(E1−Ve)/(E1−E2)=Tc(E1−Ve)/Vd  (27)

Therefore, the above-mentioned operation of the DC—DC converter inaccordance with the second embodiment is the voltage step-up andstep-down mode wherein the first switch 2 carries out the ON and OFFoperation in the ON period δ1·T and the OFF period (1−δ1)T representedby the following equations (28) and (29), respectively, and the secondswitch 5 carries out the ON and OFF operation in the ON period δ2·T andthe OFF period (1−δ2)T represented by the following equations (30) and(31), respectively.δ1·T=Td2+Tc(Ve−E2)/Vd  (28)(1−δ1)T=Tc(E1−Ve)/Vd  (29)δ2·T=Tc(Ve−E2)/Vd  (30)(1−δ2)T=Td2+Tc(E1−Ve)/Vd  (31)

The switching cycle T is the sum of the rising period Tc and thelowering period td2: (T=Tc+Td2) and becomes constant. As the directcurrent input voltage Ei becomes higher, the error voltage Ve becomeslower. By shortening the ON period δ1·T of the first switch 2 and the ONperiod δ2·T of the second switch 5, the direct current output voltage Eocan be controlled so as to stabilize.

As shown in FIG. 5( c), in the case where the direct current inputvoltage Ei is low and the error voltage Ve is higher than theoscillation voltage Vt, the output V121 of the OR circuit 121 is “H” atall times and the first switch 2 becomes in the ON state at all times.On the other hand, since the driving voltage Vg5 turns to “H” in therising period of the oscillation voltage Vt and turns to “L” in thelowering period of the oscillation voltage Vt, the second switch 5 turnsto ON state in the rising period Tc of the oscillation voltage Vt andturns to OFF state in the lowering period Td3. Therefore, theabove-mentioned operation of the DC—DC converter in accordance with thesecond embodiment is the voltage step-up mode wherein the second switch2 carries out the ON and OFF operation in the ON period δ2·T(=Tc) andthe OFF period (1−δ2)T(=Td3). The ON period δ2·T(=Tc) of the secondswitch 5 is constant, while the OFF period (1−δ2)T(=Td3) becomes shorteras the error voltage Ve rises as mentioned above. As the direct currentinput voltage Ei becomes lower, the error voltage Ve rises. Byshortening the OFF period (1−δ2)T of the second switch 2, the directcurrent output voltage Eo can be controlled so as to stabilize.

As described above, also in the DC—DC converter in accordance with thesecond embodiment, by transmitting two driving signals for carrying outthe ON and OFF operation of the first switch and the second switch,based on the comparison between one oscillation voltage waveform and oneerror voltage, the voltage step-down operation, voltage step-up andstep-down operation and voltage step-up operation can be controlled.

In the DC—DC converter in accordance with the second embodiment,frequency variation-typed control is carried out. In other words, theswitching frequency becomes higher as the direct current input voltageEi is higher than the direct current output voltage Eo in the voltagestep-down operation mode, while the switching frequency becomes higheras the direct current input voltage Ei is lower than the direct currentoutput voltage Eo in the voltage step-up operation mode. In the voltagestep-up and step-down operation mode wherein the two switches carry outthe ON and OFF operation, the switching frequency becomes lowest. Bycarrying out the frequency variation-typed control, the switching lossin the voltage step-up and step-down operation mode, which increases inthe case of the fixed frequency-typed control, can be reduced.

Although the DC—DC converter in accordance with the second embodiment iscontrolled by changing the lowering period of the oscillation voltage Vtby the error voltage Ve, likewise the DC—DC converter in accordance withthe first embodiment, it may be also controlled by changing the risingperiod of the oscillation voltage Vt by the error voltage Ve.

THIRD EMBODIMENT

FIG. 6 is a block diagram and a circuit diagram of a control section 53Bof a DC—DC converter in accordance with a third embodiment of thepresent invention. The DC—DC converter in accordance with the thirdembodiment is configured by replacing the control section 53 of theconverter section 50 shown in FIG. 1 with the above-mentioned controlsection 53B. In FIG. 6, the error amplifying circuit 10 and the pulsewidth control circuit 12 are the same as those in FIG. 2 or FIG. 4, andtherefore they are illustrated in block diagram. The same referencenumerals are applied to elements in an oscillation circuit 11B havingthe same function and configuration as those of the oscillation circuit11A shown in FIG. 4 and description thereof are omitted. The controlsection 53B of the DC—DC converter in accordance with the thirdembodiment is different from the control section 53A of the DC—DCconverter in accordance with the second embodiment shown in FIG. 4 inthat, in the oscillation circuit 11B, a circuit C1 is added to theabove-mentioned oscillation circuit 11A in FIG. 4. The configuration ofthe circuit C1 will be described below.

In the circuit C1, a third setting voltage E3 lower than the secondsetting voltage E2 is applied to the base of a PNP transistor 161. Thedirect current input voltage Ei of the direct current power source 1 isapplied to the emitter of the transistor 161 via a resistor 162. Theemitter of the transistor 161 is connected to the base of an NPNtransistor 163 and the error voltage Ve is applied to the emitter of thetransistor 163 from the error amplifying circuit 10 via a resistor 164.The direct current input voltage Ei is applied to the collector of thetransistor 163 via a PNP transistor 165. The transistors 165 and 166form a current mirror circuit and commonly connected base terminalsthereof are connected to the collector of the transistor 165. Theemitter of the transistor 166 is connected to the collector terminal andthe base terminal of an NPN transistor 167. The transistor 167 and anNPN transistor 168 form a current mirror circuit. The collector terminalof the transistor 168 is connected to the oscillation capacitor 110, andthe oscillation capacitor 110 is discharged via the transistor 168. Thegate terminal is connected to the output terminal of the NOR circuit139, and the N-channel MOSFET 169 which is driven by the output of theNOR circuit 139 is connected across the bases and emitters of thetransistor 167 and the transistor 168.

Operation of the DC—DC converter in accordance with the third embodimentconfigured above will be described referring, to FIG. 1 and FIG. 6. Inthe case where the error voltage Ve is equal to the third settingvoltage E3 or more, the operation is similar to that of theabove-mentioned DC—DC converter in accordance with the secondembodiment. Description is made as to the case where the load 8 islight, the output current is small and the error voltage Ve is lowerthan the third setting voltage E3.

In a switching converter such as a voltage step-up and step-down DC—DCconverter, wherein magnetic energy is repeatedly stored to and releasedfrom an inductor, in the case where the output current is larger than acertain value, the current flowing through the inductor does not becomezero. Such operation is referred to as a “current continuous mode”. Forexample, the input and output voltage relationship represented by theequation (Eo=δ1·Ei) in the voltage step-down operation mode isestablished in the current continuous mode. In the voltage step-downoperation mode, when the output current become smaller, the currentflowing through the inductor decreases in the OFF period of the firstswitch 2 and becomes zero soon, and the first rectifying section 3 turnsto OFF state. The operation having a period during which the currentflowing through the inductor becomes zero as mentioned above is referredto as a “current discontinuous mode”. In the current discontinuous mode,the equation (Eo=δ1·Ei) that represents the input and output voltagerelationship is not established. In order to stabilize the directcurrent output voltage Eo, the ON period (δ1·T) of the first switch 2must be made shorter as the output current becomes smaller. The DC—DCconverter in accordance with the third embodiment of the presentinvention carries out the operation of lowering the error voltage Ve.This is the same with respect to the voltage step-up operation mode andthe voltage step-up and step-down operation mode.

Power loss which is generated in the switching converter in the case ofa small output current is mainly a switching loss generated in turn-onof the switches. To reduce this switching loss thereby to improve theefficiency of the switching converter, the switching frequency should belowered in the case of a small output current.

The above-mentioned DC—DC converter in accordance with the secondembodiment operates in the voltage step-up operation mode or in thevoltage step-up and step-down operation mode when the direct currentinput voltage Ei becomes lower than the direct current output voltageEo. When the output current becomes small and the operation enters thecurrent discontinuous mode in this state, the error voltage Ve lowers,but the voltage step-up and step-down operation mode which is set at alow switching frequency is maintained. However, when the direct currentinput voltage Ei is higher than the direct current output voltage Eo,the output current becomes small and the operation enters the currentdiscontinuous mode, the error voltage Ve lowers in the voltage step-downoperation mode. At this time, the switching frequency becomes high,thereby to cause a problem of lowering the efficiency.

The DC—DC converter having the control section 53B in accordance withthe third embodiment shown in FIG. 6 is characterized in that theswitching frequency is lowered as the error voltage Ve becomes low,especially, in a light load of the voltage step-down operation mode. Theoperation will be described below.

The transistor 161 of which the third setting voltage E3 is applied tothe base terminal fixes the voltage of the base terminal of thetransistor 163 at the voltage obtained by adding the emitter-basevoltage Vd to the third setting voltage E3: (E3+Vd). When the errorvoltage Ve lowers and becomes lower than the third setting voltage E3,the voltage Vd arises as a voltage across the base and the emitter ofthe transistor 163, and the transistor 163 to which the base current issupplied via the resistor 162 turns to conducting state. Therefore, thevoltage at the emitter terminal of the transistor 163 becomes nearlyequal to the third setting voltage E3. The voltage which is a differencebetween the third setting voltage E3 and the error voltage Ve: (E3−Ve)is applied to the resistor 164. When it is assumed that the resistancevalue of the resistor 164 is R164, the current I4 flowing to theresistor 164 through the transistor 163 is represented by the followingequation (32).I4=(E3−Ve)/R164  (32)

This current I4 is the discharge current of the oscillation capacitor110 flowing through the current mirror circuit formed of the transistor165 and the transistor 166 and the current mirror circuit formed of thetransistor 167 and the transistor 168. The FET 169 turns ON when theoutput of the NOR circuit 139 is “H”, thereby the current mirror circuitformed of the transistor 167 and the transistor 168 turns to OFF state.In other words, the transistor 168 turns to ON state and the dischargecurrent I4 flows in the rising period of the oscillation voltage Vtduring which the output of the NOR circuit 139 turns to “L”. Thedischarge current I4 is set so as to be smaller than the charge currentI1 from the transistor 113. The charge current in the rising period ofthe oscillation voltage Vt is the difference between the charge currentI1 and the discharge current I4: (I1−I4).

The discharge current I4 becomes larger as the error voltage Ve becomeslower than the third setting voltage E3. Therefore, the charge currentin the rising period of the oscillation voltage Vt becomes smaller asthe error voltage Ve becomes lower than the third setting voltage E3.For that reason, the rising period of the oscillation voltage Vt, thatis, the OFF period of the first switch 2 in the voltage step-downoperation mode becomes longer as the error voltage Ve becomes lower thanthe third setting voltage E3, and as a result the switching frequencylowers.

As mentioned above, in the DC—DC converter in accordance with the thirdembodiment of the present invention, in addition to the above-mentionedfeature described in the second embodiment, in the case where the loadis light and the output current is small in the voltage step-downoperation mode, since the switching frequency lowers as the errorvoltage Ve lowers, the switching loss is reduced, and it is possible toobtain an effect of improving the efficiency.

FOURTH EMBODIMENT

FIG. 7 is a circuit diagram of a control section 53C of a DC—DCconverter in accordance with a fourth embodiment of the presentinvention. The DC—DC converter in accordance with the fourth embodimentis configured by replacing the control section 53 of the convertersection 50 shown in FIG. 1 with the above-mentioned control section 53C.In FIG. 7, the same reference numerals are applied to elements havingthe same function and configuration as those of the control section 53Bof the DC—DC converter in accordance with the third embodiment shown inFIG. 6 and description thereof are omitted. The control section 53C ofthe DC—DC converter in accordance with the fourth embodiment isdifferent from the control section 53B of the DC—DC converter inaccordance with the third embodiment shown in FIG. 6 in that a circuitC2 is added to the above-mentioned oscillation circuit 11B of FIG. 6 forthe oscillation circuit 11C. The configuration of the circuit C2 will bedescribed below.

The base terminal of an NPN transistor 170, which is connected to thedirect current power source 1 of the input voltage Ei at the collectionterminal is connected to the junction of the resistor 114 and the diode115. The emitter terminal of the transistor 170 is connected to the baseof the transistor 161 and the collector terminal of an NPN transistor172 via a resistor 171. A transistor 172 and an NPN transistor 173 forma current mirror circuit, and the collector terminal of the transistor173 is connected to base terminal thereof and also connected to thedirect current power source 1 via a resistor 174.

When the value of resistance of the resistor 114 is made equal to thatof the resistor 116, the first setting voltage E1 and the second settingvoltage E2 are represented by the equations (33) and (34), respectively.E1=(Ei+Vd)/2  (33)E2=(Ei−Vd)/2  (34)

As described in the second embodiment, the ON period δ1·T and the OFFperiod (1−δ1)T of the first switch 2 in the current continuous mode arerepresented by the following equations (35) and (36), respectively.δ1·T=Td1=C·Vd/{I2+(E2−Ve)/R131}  (35)(1−δ1)T=Tc=C·Vd/I1  (36)

Since the duty ratio δ1 is equal to the ratio of the direct currentoutput voltage Eo and the direct current input voltage Ei: (Eo/Ei), theerror voltage Ve is obtained as represented by an equation (37) byarranging each of the above-mentioned equations.Ve=E2−R131·{(Ei/Eo)·I1−I1−I2}  (37)

In the DC—DC converter in accordance with the fourth embodiment, thesecond setting voltage E2 has input-voltage dependency because thesecond setting voltage E2 is obtained from the direct current inputvoltage Ei. Therefore, it is impossible to know the input-voltagedependency of the error voltage Ve. However, during the operation ofstabilizing the direct current output voltage Eo, the error voltage Vein the voltage step-down operation mode and the current continuous modebecomes close to the second setting voltage E2 as the direct currentinput voltage Ei becomes high. When the load becomes light and theoperation enters the current discontinuous mode, the error voltage Ve islower than the value given by the equation (37). In other words, whenthe third setting voltage E3 is a fixed value, the load that beginslowering of the switching frequency becomes small as the direct currentinput voltage E1 becomes low. In a range in which the switchingfrequency does not lower, only the ON periods of the first switch 2 andthe second switch 5 are made small, whereby the switching frequencyremains high. Hence, it is found that input dependency should beprovided so that the third setting voltage E3 becomes high as the directcurrent input voltage becomes low, by setting the third setting voltageE3 at a value slightly lower than the value obtained by the equation(32) in the second embodiment.

In the oscillation circuit 11C of the DC—DC converter shown in FIG. 7,description is made as to a circuit C2 for obtaining the third settingvoltage E3. When it is assumed that the resistance value of the resistor174 is R174, the current I5 flowing to the transistor 173 through theresistor 174 is represented by the following equation (38).I5=(Ei−Vd)/R174  (38)

Since this current I5 flows to the resistor 171 through the transistor172 of the current mirror circuit, when it is assumed that theresistance value of the resistor 171 is R171, voltage drop thereof isrepresented by the following equation (39).(R171/R174)·(Ei−Vd)  (39)

On the other hand, since the emitter terminal of the transistor 170connected to the resistor 171 has a value obtained by subtracting thebase-emitter voltage Vd of the transistor 170 from the first settingvoltage E1: (E1−Vd), it becomes equal to the second setting voltage E2as represented by the following equation (40).E1−Vd=E2  (40)

Therefore, the third setting voltage E3 is represented by the followingequation (41).E3=E2−(R171/R174)·(Ei−Vd)  (41)

Where, the resistance ratio R171/R174 is set to be equal to the voltageratio R131·I1/Eo, and the voltage (R171/R174)·Vd is set to be slightlysmaller than the voltage R131·(I1+I2). Consequently, the third settingvoltage E3 is set at a value slightly lower than the value representedby the equation (37) of the error voltage Ve in the voltage step-downoperation mode and the current continuous mode.

The DC—DC converter in accordance with the fourth embodiment has alsothe features in the third embodiment in addition to the features of inthe second embodiment. That is, in the case where the load is light andthe output current is small in the voltage step-down operation mode, theswitching frequency lowers as the error voltage Ve lowers. Thenswitching loss decreases, whereby the efficiency can be improved.Furthermore, by changing the third setting voltage in response to thedirect current input voltage Ei, the output current that begins loweringof the switching frequency can be prevented from depending on the changeof the direct current input voltage Ei, and be set at the value slightlysmaller than the output current in the current discontinuous mode.

FIFTH EMBODIMENT

In the above-mentioned first embodiment and the second embodiment, theerror voltage Ve is compared with the first setting voltage E1 and thesecond setting voltage E2, and the operation mode is changed at eachcoincidence point. For example, in the case where the error voltage Veis between the first setting voltage E1 and the second setting voltageE2, and where the error voltage Ve rises and reaches the first settingvoltage E1 as the direct current input voltage Ei lowers, the voltagestep-up and step-down operation mode is switched to the voltage step-upoperation mode. When it is assumed that, with this switching of theoperation mode, the number of switches that carry out the ON and OFFoperation decreases and the power consumption of the DC—DC converter isreduced slightly, the direct current output voltage Eo rises inaccordance with the reduction. Consequently, the error voltage Ve lowersso that the raised direct current output voltage Eo is made equal to adesired value. In the case where the lowered error voltage Ve returns tothe first setting voltage E1, the voltage step-up operation mode isswitched to the voltage step-up and step-down operation mode. At thistime, the power consumption of the DC—DC converter increases slightly,the direct current output voltage Eo lowers in accordance with theincrease, and the error voltage Ve rises, whereby the voltage step-upand step-down operation mode is switched to the voltage step-upoperation mode again. When the above-mentioned operation is repeated,the operation mode is not stable, and it is conceivable of theoccurrence of harmful influences such as increase in output ripplevoltage and occurrence of noise. As a means to prevent such phenomena,it is desirable that the operation of comparing the error voltage Vewith the first setting voltage E1 have a hysteresis. This is similarwith respect to the operation of comparing the error voltage Ve with thesecond setting voltage E2.

FIG. 8 is a circuit diagram showing the configuration of an oscillationcircuit 11D of a control section 53D of a DC—DC converter in accordancewith a fifth embodiment of the present invention. The DC—DC converter inaccordance with the fifth embodiment is configured by replacing thecontrol section 53 of the converter section 50 shown in FIG. 1 with theabove-mentioned control section 53D. The DC—DC converter in accordancewith the fifth embodiment is different from the control section 53 ofthe DC—DC converter in accordance with the first embodiment shown inFIG. 2 in the oscillation circuit 11D. Fundamental configuration andoperation other than the oscillation circuit 11D is the same. In theoscillation circuit 11D shown in FIG. 8, the same reference numerals areapplied to elements having the same function and configuration as thoseof the oscillation circuit 11 shown in FIG. 2 and descriptions thereofare omitted.

In the oscillation circuit 11D which is a different part from theconfiguration of the control section 53 of the DC—DC converter of thefirst embodiment shown in FIG. 2 in the control section 53D of FIG. 8, acircuit C3 is further added to the configuration of the oscillationcircuit 11 shown in FIG. 2. The configuration of the circuit C3 will bedescribed below.

A comparator 147 compares the first setting voltage E1 with the errorvoltage Ve, and a comparator 148 compares the second setting voltage E2with the error voltage Ve. An N-Channel MOSFET 149 receives the outputof the comparator 147 at the gate terminal thereof and turns to ONstate, when the first setting voltage E1 is larger than the errorvoltage Ve: (E1>Ve) and the output of the comparator 147 turns to “H”.Furthermore, a N-Channel MOSFET 170 receives the output of thecomparator 148 at the gate terminal thereof and turns to ON state, whenthe second setting voltage E2 is smaller than the error voltage Ve:(E2<Ve) and the output of the comparator 148 turns to “H”. Further, theoscillation circuit 11D of the fifth embodiment is provided with aconstant current power source 151 and supplies the constant current I3to the base terminal of the NPN transistor 118 through an FET 149 and anFET 170.

In the oscillation circuit 11D of the DC—DC converter in accordance withthe fifth embodiment configured as mentioned above, when the errorvoltage Ve is between the first setting voltage E1 and the secondsetting voltage E2, that is, in the voltage step-up and step-downoperation mode, both the FET 149 and the FET 170 turn to ON state andthe constant current I3 is supplied to the base terminal of the NPNtransistor 118. Since the NPN transistor 118 and the NPN transistor 117form a current mirror circuit, this constant currant I3 is added to thedischarge current of the oscillation capacitor 110. During this period,the oscillation capacitor 110 is in the charge period during which theoscillation voltage Vt is in the rising period, and the charge currentis a current obtained by subtracting the current I3 of the constantcurrent source 151 from the current I1 of the constant current source111: (I1−I3).

Next, when the error voltage Ve rises and reaches the first settingvoltage E1 as the direct current input voltage Ei lowers, the operationin the case where the voltage step-up and step-down operation mode isswitched to the voltage step-up operation mode is described.

In the voltage step-up and step-down operation mode as mentioned above,since the charge current of the oscillation capacitor 110 is the current(I1−I3), the rising period Tc of the oscillation voltage Vt isrepresented by the following equation (42).Tc=C·Vd/(I1−I3)  (42)

When the error voltage Ve approaches the first setting voltage E1 inthis state, the OFF time of the first switch 2 becomes approximatelyzero and the ON time of the second switch 5 becomes close to the risingperiod Tc.

When the error voltage Ve reaches the first setting voltage E1, theoutput of the comparator 147 is inverted to “L”. For that reason, theFET 149 turns to OFF state, and the current I3 from the constant currentsource 151 does not flow, and at the same time, the first switch 2 turnsto ON state at all times, and the operation enters the voltage step-upoperation mode. At this time, the ON time of the second switch 5 ischanged from the value represented by the equation C·Vd/(I1−I3) to thevalue represented by the equation C·Vd/I1 and becomes short. Since thisis in the direction which lowers the direct current output voltage Eo,the error voltage Ve rises further and the operation in the voltagestep-up operation mode is established.

Next, when the error voltage Ve lowers and reaches the second settingvoltage E2 as the direct current input voltage Ei rises, the operationin the case where the voltage step-up and step-down operation mode isswitched to the voltage step-down operation mode is described.

During operation in the voltage step-up and step-down operation mode,the rising period Tc of the oscillation voltage Vt is represented by thefollowing equation (43).Tc=C·Vd/(I1−I3)  (43)

When the error voltage Ve approaches the second setting voltage E2 inthis state, the OFF time of the first switch 2 approaches the risingperiod Tc, and the ON time of the second switch 5 becomes approximatelyzero.

When the error voltage Ve reaches the second setting voltage E2, theoutput of the comparator 148 is inverted to “L”. Hence, the FET 170turns to OFF state and the current I3 from the constant current source151 does not flow. At this time, the second switch 5 turns to OFF stateat all times and the operation enters the voltage step-down operationmode. At this time, the OFF time of the first switch 2 is changed fromthe value represented by the equation C·Vd/(I1−I3) to the valuerepresented by the equation C·Vd/I1 and becomes short. Since this is inthe direction which raises the direct current output voltage Eo, theerror voltage Ve lowers further and the operation in the voltagestep-down operation mode is established.

As mentioned above, according to the DC—DC converter in accordance withthe fifth embodiment, the operation mode can be switched smoothly. Ithas the effect of carrying out the stable switching operation,especially when the voltage step-up and step-down operation mode isswitched to the voltage step-up operation mode. This is an effectivemeasure against phenomenon that occurs as a result of reduction inswitching loss caused by decreasing the number of switches for carryingout the ON-OFF operation in switching to the voltage step-up operationmode. In other words, it is possible to prevent the phenomenon whereinthe operation mode changes suddenly to become unstable, for example,when the direct current output voltage Eo rises, the error voltage Velowers and the operation returns the voltage step-up and step-downoperation mode again, and further shifts to the voltage step-upoperation mode.

SIXTH EMBODIMENT

The above-mentioned method for switching the operation mode smoothly asdescribed in the fifth embodiment also is applicable to the DC—DCconverter in accordance with the second embodiment shown in FIG. 4.

FIG. 9 is a circuit diagram showing the configuration of a controlsection 53E of a DC—DC converter in accordance with a sixth embodimentof the present invention. The DC—DC converter in accordance with thesixth embodiment is configured by replacing the control section 53 ofthe converter section 50 shown in FIG. 1 with the above-mentionedcontrol section 53E. In the sixth embodiment, the method for switchingthe operation mode smoothly as described in the fifth embodiment isapplied to the oscillation circuit 11A of the DC—DC converter inaccordance with the second embodiment shown in FIG. 4.

Fundamental configuration and operation of the control section 53Eincluding the oscillation circuit 11E of the DC—DC converter shown inFIG. 9 is the same as that of the control section 53 in accordance withthe second embodiment shown in FIG. 4, and the same reference numeralsare applied to elements having the same function and configuration anddescriptions thereof are omitted.

The difference between the control section 53E of the DC—DC converter inaccordance with the sixth embodiment shown in FIG. 9 and the controlsection 53A of the DC—DC converter shown in FIG. 4 is in the oscillationcircuit 11E. The oscillation circuit 11E is configured by adding acircuit C4 to the oscillation circuit 11A shown in FIG. 4. Theconfiguration and operation of the circuit C4 will be described below.

A comparator 152 compares the first setting voltage E1 with the errorvoltage Ve, and a comparator 153 compares the second setting voltage E2with the error voltage Ve. An N-Channel MOSFET 154, receives the outputof the comparator 152 at the gate terminal thereof, and turns to ONstate when the first setting voltage E1 is smaller than the errorvoltage Ve: (E1<Ve), and the output of the comparator 152 turns to “H”.An N-Channel MOSFET 155, the gate terminal of which receives the outputof the comparator 153, turns to ON state when the second setting voltageE2 is larger than the error voltage Ve: (E2>Ve) and the output of thecomparator 153 becomes “H”. Furthermore, the control section of theDC—DC converter in FIG. 9 is provided with a constant current source156, and a constant current I4 is supplied to the base terminal of theNPN transistor 118 via a parallel circuit formed of an FET 154 and anFET 155.

By the configuration as mentioned above, during operation in the voltagestep-up operation mode or the voltage step-down operation mode, theconstant current I4 is supplied to the base terminal of the NPNtransistor 118 and is added to the discharge current of the oscillationcapacitor 110.

The period during which the constant current I4 is added to thedischarge current of the oscillation capacitor 110 is set to be thelowering period of the oscillation voltage Vt, whereby the DC—DCconverter in accordance with the second embodiment has a similar effectto the DC—DC converter in accordance with the first embodiment asdescribed in FIG. 8.

In the above-mentioned first embodiment to sixth embodiment, the risingperiod may be controlled by changing depending on the error voltage Ve,and the lowering period may be controlled by changing depending on theerror voltage Ve.

INDUSTRIAL APPLICABILITY

As clarified by the detailed description of each embodiment, the presentinvention has the following effects.

In the DC—DC converter of the present invention, control from voltagestep-up to voltage step-up and step-down and further to voltagestep-down is carried out with two driving signals that are generated bycomparing the waveform of one oscillation voltage with one error voltageand perform the ON and OFF operation of the first, and second switches.Hence, it is possible to control the voltage step-down operation mode,the voltage step-up and step-down operation mode and the voltage step-upoperation mode, whereby the configuration of the control section can besimplified.

In the voltage step-down operation or the voltage step-up operation, asthe difference between input voltage and output voltage becomes large,the switching frequency is made high and the switching frequency is madelower in the voltage step-up and step-down operation. Hence, theswitching loss due to the ON and OFF operation of the two switches inthe voltage step-up and step-down operation can be reduced.

In the voltage step-down operation in which the switching frequencyfluctuates as mentioned above, in the case where the third settingvoltage is provided and the error voltage makes the direct currentoutput voltage low beyond the third setting voltage, the switchingfrequency is made low as the difference between input voltage and outputvoltage becomes large. Hence, in the case where the load is light andthe output current is small, the switching loss can be reduced.

By providing the above-mentioned third setting voltage with directcurrent voltage dependency, the point at which the operation enters thecurrent discontinuous mode and the switching frequency lowers can beprevented from fluctuating depending on the change of the direct currentinput voltage.

By changing the rising or lowering speed of the oscillation voltage inthe direction of facilitating the shift of operation mode in switchingthe operation mode, the DC—DC converter of the present invention has theeffect that the operation mode can shift smoothly.

1. A DC—DC converter of voltage step-up and step-down type comprising avoltage step-down converter section having a first switch, a voltagestep-up converter section having a second switch and a control sectionfor turning ON and OFF said first switch and said second switch,respectively, for receiving a direct current input voltage andoutputting a direct current output voltage to a load, wherein saidcontrol section comprises: an error amplifying circuit for comparingsaid direct current output voltage with a predetermined voltage and foroutputting an error voltage, an oscillation circuit for generating anoscillation voltage cyclically changing between a first setting voltageand a second setting voltage lower than said first setting voltage, aratio of rising period or a ratio of lowering period per one cycle ofsaid oscillation voltage increasing as the difference between said errorvoltage and said first setting voltage increases, when said errorvoltage is higher than said first setting voltage, and the ratio ofrising period or the ratio of lowering period per one cycle of saidoscillation voltage increasing as the difference between said errorvoltage and said second setting voltage increases, when said errorvoltage is lower than said second setting voltage, and a pulse widthcontrol circuit for controlling the ON and OFF periods of said firstswitch and the ON and OFF periods of said second switch so as to carryout control of a voltage step-down operation mode wherein said secondswitch is fixed at OFF state and said first switch is turned ON and OFF,or to carry out control of a voltage step-up operation mode wherein saidfirst switch is fixed to ON state and said second switch is turned ONand OFF, in a case where said error voltage is compared with saidoscillation voltage and said error voltage does not coincide with saidoscillation voltage, and to carry out control of a voltage step-up andstep-down operation mode wherein both said first switch and said secondswitch are turned ON and OFF in a case where said error voltagecoincides with said oscillation voltage occasionally.
 2. A DC—DCconverter in accordance with claim 1, wherein said error amplifyingcircuit is configured: to output the error voltage that rises as saiddirect current output voltage is lower than said predetermined voltage,and lowers as said direct current output voltage is higher than saidpredetermined voltage, said oscillation circuit is configured: toincrease the ratio of rising period per one cycle of said oscillationvoltage as the difference between said error voltage and said secondsetting voltage increases when said error voltage is lower than saidsecond setting voltage, and to increase the ratio of rising period perone cycle of said oscillation voltage as the difference between saiderror voltage and said first setting voltage increases when said errorvoltage higher than said first setting voltage, and said pulse widthcontrol circuit is configured: to carry out control in the voltagestep-down operation mode wherein said second switch is fixed at OFFstate, and said first switch is turned to OFF state in the rising periodof said oscillation voltage and turned to ON state in the remainingperiod, in a case where said error voltage is lower than said secondsetting voltage, in a case where said error voltage is higher than saidfirst setting voltage, to carry out control in the voltage step-upoperation mode wherein said first switch is fixed at ON state, and saidsecond switch is turned to ON state in the rising period of saidoscillation voltage and turned to OFF state in the remaining period, andin the case where said error voltage coincides with said oscillationvoltage occasionally, to carry out control in the voltage step-up andstep-down operation mode wherein said first switch is turned to OFFstate in the period during which said error voltage is lower than saidoscillation voltage in the rising period of said oscillation voltage andturned to ON state in the remaining period, and said second switch isturned to ON state in the period during which said error voltage ishigher than said oscillation voltage in the rising period of saidoscillation voltage and turned to OFF state in the remaining period. 3.A DC—DC converter in accordance with claim 2, wherein said oscillationcircuit is configured: to have an oscillation capacitor for outputtingsaid oscillation voltage by being charged or discharged in response to apulse signal having a predetermined cycle, and to charge saidoscillation capacitor when said pulse signal is input in a state whereinsaid oscillation voltage is maintained at said second setting voltage,to discharge said oscillation capacitor when said oscillation voltagereaches said first setting voltage, and to maintain said oscillationvoltage in the vicinity of said second setting voltage without chargingor discharging said oscillation capacitor when said oscillation voltagereaches said second setting voltage.
 4. A DC—DC converter in accordancewith claim 1, wherein said oscillation circuit is configured: togenerate a triangular wave shaped oscillation voltage that rises orlowers cyclically between the first setting voltage and the secondsetting voltage lower than said first setting voltage, the cycle of saidoscillation voltage decreasing as the difference between said errorvoltage and said first setting voltage increases, when said errorvoltage is higher than said first setting voltage, and the cycle of saidoscillation voltage decreasing as the difference between said errorvoltage and said second setting voltage increases when said errorvoltage is lower than said second setting voltage.
 5. A DC—DC converterin accordance with claim 4, wherein said error amplifying circuit isconfigured: to output the error voltage that rises as said directcurrent output voltage becomes lower than said predetermined voltage,and lowers as said direct current output voltage becomes higher thansaid predetermined voltage, said oscillation circuit is configured: toincrease the ratio of rising period per one cycle of said oscillationvoltage as the difference between said error voltage said second settingvoltage increases, when said error voltage lower than said secondsetting voltage and to increase the ratio of rising period per one cycleof said oscillation voltage as the difference between said error voltageand said first setting voltage increases, when said error voltage ishigher than said first setting voltage, and said pulse width controlcircuit is configured: to carry out control in the voltage step-downoperation mode wherein said second switch is fixed at OFF state, andsaid first switch is turned to OFF state in the rising period of saidoscillation voltage and turned to ON state in the remaining period in acase where said error voltage is lower than said second setting voltage,in a case where said error voltage is higher than said first settingvoltage, to carry out control in the voltage step-up operation modewherein said first switch is fixed at ON state, and said second switchis turned to ON state in the rising period of said oscillation voltageand turned to OFF state in the remaining period, and in the case wheresaid error voltage coincides with said oscillation voltage occasionally,to carry out control in the voltage step-up and step-down operation modewherein said first switch is turned to OFF state in the period duringwhich said error voltage is lower than said oscillation voltage in therising period of said oscillation voltage and turned to ON state in theremaining period, and said second switch is turned to ON state in theperiod during which said error voltage is higher than said oscillationvoltage in the rising period of said oscillation voltage and turned toOFF state in the remaining period.
 6. A DC—DC converter in accordancewith claim 5, wherein said oscillation circuit is configured: to set therising speed of said oscillation voltage constant regardless of thechange of said error voltage, and to increase the lowering speed of saidoscillation voltage as said error voltage is higher than said firstsetting voltage, and as said error voltage is lower than said secondsetting voltage, and said pulse width control circuit is configured: inthe lowering period of said oscillation voltage, to turn said firstswitch to ON state and to turn said second switch to OFF state, and inthe rising period of said oscillation voltage, to turn both said firstswitch and said second switch to ON state in a case where said errorvoltage is higher than said oscillation voltage, and to turn both saidfirst switch and said second switch to OFF state in a case where saiderror voltage is lower than said oscillation voltage.
 7. A DC—DCconverter in accordance with claim 4, wherein said error amplifyingcircuit is configured: to output the error voltage that rises as saiddirect current output voltage is lower than said predetermined voltage,and lowers as said direct current output voltage is higher than saidpredetermined voltage, said oscillation circuit is configured: to setthe lowering speed of said oscillation voltage constant regardless ofthe change of said error voltage and to increase the rising speed ofsaid oscillation voltage as said error voltage is higher than said firstsetting voltage, and as said error voltage is lower than said secondsetting voltage, and said pulse width control circuit is configured: inthe rising period of said oscillation voltage, to turn said first switchto ON state and to turn said second switch to OFF state, and in thelowering period of said oscillation voltage, to turn both said firstswitch and said second switch to ON state in a case where said errorvoltage is higher than said oscillation voltage, and to turn both saidfirst switch and said second switch to OFF state in a case where saiderror voltage is lower than said oscillation voltage.
 8. A DC—DCconverter in accordance with claim 4, wherein said oscillation circuitis configured: so as to elongate the cycle of said oscillation voltageas the voltage difference between said error voltage and said thirdsetting voltage becomes large in said voltage step-down operation modein a case where a predetermined third setting voltage is compared withsaid error voltage said error voltage exceeds said third setting voltagein the direction of lowering said direct current output voltage.
 9. ADC—DC converter in accordance with claim 5, wherein said oscillationcircuit is configured: with respect to the third setting voltage lowerthan said second setting voltage, so as to elongate the cycle of saidoscillation voltage as the voltage difference between said error voltageand said third setting voltage becomes large in a case where said errorvoltage is lower than said third setting voltage.
 10. A DC—DC converterin accordance with claim 6, wherein said oscillation circuit isconfigured: with respect to the third setting voltage lower than saidsecond setting voltage, so as to slow the lowering speed of saidoscillation voltage as the voltage difference between said error voltageand said third setting voltage becomes large in a case where said errorvoltage is lower than said third setting voltage.
 11. A DC—DC converterin accordance with claim 7, wherein said oscillation circuit isconfigured: with respect to the third setting voltage lower than saidsecond setting voltage, so as to slow the rising speed of saidoscillation voltage as the voltage difference between said error voltageand said third setting voltage becomes large in a case where said errorvoltage is lower than said third setting voltage.
 12. A DC—DC converterin accordance with claim 9, wherein said third setting voltage is set soas to be close to said second setting voltage as said direct currentinput voltage lowers.
 13. A DC—DC converter in accordance with claim 1,wherein said control section has a predetermined hysteresischaracteristic in the operation of comparing said error voltage withsaid first setting voltage.
 14. A DC—DC converter in accordance withclaim 2, wherein said oscillation circuit is configured so as to makesmall the ratio of the rising period per one cycle of said oscillationvoltage when said error voltage becomes higher than said first settingvoltage.
 15. A DC—DC converter in accordance with claim 1, wherein saidcontrol section has a predetermined hysteresis characteristic in theoperation of comparing said error voltage with said second settingvoltage.
 16. A DC—DC converter in accordance with claim 2, wherein saidoscillation circuit is configured so as to make small the ratio of therising period per one cycle of said oscillation voltage when said errorvoltage becomes lower than said second setting voltage.